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參數(shù)資料
| 型號： | P83CE598FFB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit microcontroller with CAN controller(帶CAN控制器的8位微控制器) |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 31/108頁 |
| 文件大小： | 661K |
| 代理商： | P83CE598FFB |
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1996 Jun 27
31
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
13.5
Control Segment and Message Buffer
description
The CAN-Controller appears to the CPU as a
memory-mapped peripheral, guaranteeing the
independent operation of both parts.
13.5.1
A
DDRESS ALLOCATION
The address area of the CAN-controller consists of the
Control Segment and the message buffers. The Control
Segment is programmed during an initialization down-load
in order to configure communication parameters (e.g. bit
timing). The communication over the CAN-bus is also
controlled via this segment by the CPU. A message which
is to be transmitted, must be written to the Transmit Buffer.
After a successful reception the CPU may read the
message from the Receive Buffer and then release it for
further use.
13.5.2
C
ONTROL
S
EGMENT LAYOUT
The exchange of status, control and command signals
between the CPU and the CAN-controller is performed in
the control segment. The layout of this segment is shown
in Fig.15. After an initial down-load, the contents of the
registers Acceptance Code, Acceptance Mask,
Bus Timing 0, Bus Timing 1 and Output Control should not
be changed. These registers may only be accessed when
the Reset Request bit in the Control Register is set HIGH
(see Tables 30, 31 and 32).
handbook, full pagewidth
01H
02H
03H
04H
05H
06H
07H
08H
09H
ADDRESS
1
2
3
4
5
6
7
8
9
control segment
MGA160 - 1
CONTROL
COMMAND
STATUS
INTERRUPT
ACCEPTANCE CODE
ACCEPTANCE MASK
BUS TIMING 0
BUS TIMING 1
OUTPUT CONTROL
TEST
descriptor
data field
transmit buffer
descriptor
data field
receive buffer 0 or 1
10
11
12
13
14
15
16
17
18
19
IDENTIFIER,
RTR BIT, DATA LENGTH CODE
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
BYTE 8
20
21
22
23
24
25
26
27
28
29
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
11H
12H
13H
IDENTIFIER,
RTR BIT, DATA LENGTH CODE
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
BYTE 8
IDENTIFIER,
RTR BIT, DATA LENGTH CODE
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
BYTE 8
0AH
0BH
0CH
0DH
0EH
0FH
10H
Fig.15 CAN-controller internal address allocation.
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