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參數(shù)資料
| 型號(hào)： | P83CE598FFB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit microcontroller with CAN controller(帶CAN控制器的8位微控制器) |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 54/108頁 |
| 文件大?。?/td> | 661K |
| 代理商： | P83CE598FFB |
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1996 Jun 27
54
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
13.5.19.3 Time Segment 2 (TSEG2)
This time segment provides:
additional time at the sample point for calculation of the
subsequent bit levels (e.g. arbitration)
synchronization buffer segment directly after the sample
point.
TSEG2 is programmable from 1 to 8 system clock cycles
(see Section 13.5.10.
13.5.19.4 Synchronisation Jump Width (SJW)
SJW defines the maximum number of clock cycles (t
SCL
) a
period may be reduced or increased by one
resynchronization. SJW is programmable from 1 to 4
system clock cycles, see Section 13.5.2.
13.5.19.5 Propagation Delay Time (t
prop
)
The Propagation Delay Time is:
t
prop
2
physical bus delay
input comparator delay
output driver delay
+
t
prop
is rounded up to the nearest multiple of t
SCL
.
13.5.19.6 Bit Timing Restrictions
Restrictions on the configuration of the bit timing are based
on internal processing. The restrictions are:
t
TSEG2
≥
2t
SCL
t
TSEG2
≥
t
SJW
t
TSEG1
≥
t
SEG2
t
TSEG1
≥
t
SJW
+ t
prop
.
The three sample mode (SAM = HIGH) has the effect of
introducing a delay of one system clock cycle on the
bus-line. This must be taken into account for the correct
calculation of TSEG1 and TSEG2:
t
TSEG1
≥
t
SJW
+ t
prop
+ 2t
SCL
t
TSEG2
≥
3t
SCL
.
13.5.20 S
YNCHRONIZATION
Synchronization is performed by a state machine which
compares the incoming edge with its actual bit timing and
adapts the bit timing by hard synchronization or
resynchronization.
+
(
)
×
.
=
This type of synchronization occurs only at the beginning
of a message.
The CAN-controller synchronizes on the first incoming
recessive-to-dominant edge of a message (being the
leading edge of a message's Start-Of-Frame bit;
see Section 13.6.2.
Resynchronization occurs during the transmission of a
message's bit stream to compensate for:
Variations in individual CAN-controller oscillator
frequencies
Changes introduced by switching from one transmitter
to another (e.g. during arbitration).
As a result of resynchronization either t
TSEG1
may be
increased by up to a maximum of t
SJW
or t
TSEG2
may be
decreased by up to a maximum of t
SJW
:
t
TSEG1
≤
t
SCL
[(TSEG1 + 1) + (SJW + 1)]
t
TSEG2
≥
t
SCL
[(TSEG2 + 1)
(SJW + 1)].
TSEG1, TSEG2 and SJW are the programmed numerical
values.
The phase error (e) of an edge is given by the position of
the edge relative to SYNCSEG, measured in system clock
cycles (t
SCL
).
The value of the phase error is defined as:
e = 0, if the edge occurs within SYNCSEG
e
>
0, if the edge occurs within TSEG1
e
<
0, if the edge occurs within TSEG2.
The effect of resynchronization is:
The same as that of a hard synchronization, if the
magnitude of the phase error (e) is less or equal to the
programmed value of t
SJW
To increase a bit period by the amount of t
SJW
,if the
phase error is positive and the magnitude of the phase
error is larger than t
SJW
To decrease a bit period by the amount of t
SJW
if the
phase error is negative and the magnitude of the phase
error is larger than t
SJW
.
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