參數(shù)資料
型號: P89LPC902FD,112
廠商: NXP Semiconductors
文件頁數(shù): 53/53頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 1K 8-SOIC
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 1
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 7.3728MHz
外圍設(shè)備: 欠壓檢測/復(fù)位,LED,POR,WDT
輸入/輸出數(shù): 6
程序存儲器容量: 1KB(1K x 8)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 剪切帶 (CT)
配用: 622-1006-ND - SOCKET ADAPTER BOARD
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-1995-1
Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 05 — 17 December 2004
9 of 53
9397 750 14465
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P1.0 to P1.5
Port 1: Port 1 is an I/O port with a user-congurable output type. During reset Port 1
latches are congured in the input only mode with the internal pull-up disabled. The
operation of the congurable Port 1 pins as inputs and outputs depends upon the
port conguration selected. Each of the congurable port pins are programmed
electrical characteristics” for details. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
5
I/O
P1.2 — Port 1 bit 2.
O
T0 — Timer/counter 0 external count input or overow output.
4I
P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specied level.
When system power is removed VDD will fall below the minimum specied
operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specied operating voltage.
Also used during a power-on sequence to force In-System Programming mode.
P3.0 to P3.1
I/O
Port 3: Port 3 is an I/O port with a user-congurable output types. During reset Port 3
latches are congured in the input only mode with the internal pull-up disabled. The
operation of port 3 pins as inputs and outputs depends upon the port conguration
selected. Each port pin is congured independently. Refer to Section 8.12.1 “Port
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described below:
3
I/O
P3.0 — Port 3 bit 0.
O
XTAL2 — Output from the oscillator amplier (when a crystal oscillator option is
selected via the FLASH conguration).
O
CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK to TRIM.6). It
can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source
for the real time clock/system timer.
2
I/O
P3.1 — Port 3 bit 1.
I
XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when
selected via the FLASH conguration). It can be a port pin if internal RC oscillator or
Watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not
used to generate the clock for the real time clock/system timer.
VSS
8I
Ground: 0 V reference.
VDD
1I
Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.
Table 3:
P89LPC901 pin description…continued
Symbol
Pin
Type
Description
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