參數(shù)資料
型號: P89LPC938FDH,529
廠商: NXP Semiconductors
文件頁數(shù): 17/68頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 28-TSSOP
產品培訓模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝: 51
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,LED,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據轉換器: A/D 8x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 管件
產品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1011-ND - BOARD FOR LPC938 TSSOP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱: 568-2013-5
935278546529
P89LPC938FDH-S
PIC18F87J90 FAMILY
DS39933D-page 24
2010 Microchip Technology Inc.
PORTD is a bidirectional I/O port.
RD0/SEG0/CTPLS
RD0
SEG0
CTPLS
72
I/O
O
ST
Analog
ST
Digital I/O.
SEG0 output for LCD.
CTMU pulse generator output.
RD1/SEG1
RD1
SEG1
69
I/O
O
ST
Analog
Digital I/O.
SEG1 output for LCD.
RD2/SEG2
RD2
SEG2
68
I/O
O
ST
Analog
Digital I/O.
SEG2 output for LCD.
RD3/SEG3
RD3
SEG3
67
I/O
O
ST
Analog
Digital I/O.
SEG3 output for LCD.
RD4/SEG4
RD4
SEG4
66
I/O
O
ST
Analog
Digital I/O.
SEG4 output for LCD.
RD5/SEG5
RD5
SEG5
65
I/O
O
ST
Analog
Digital I/O.
SEG5 output for LCD.
RD6/SEG6
RD6
SEG6
64
I/O
O
ST
Analog
Digital I/O.
SEG6 output for LCD.
RD7/SEG7
RD7
SEG7
63
I/O
O
ST
Analog
Digital I/O.
SEG7 output for LCD.
TABLE 1-4:
PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST
= Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
I2C = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
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