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參數(shù)資料
| 型號： | P89LPC938FDH,529 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 68/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 8K 28-TSSOP |
| 產(chǎn)品培訓模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標準包裝： | 51 |
| 系列： | LPC900 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 18MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復位，LED，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 26 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 512 x 8 |
| RAM 容量： | 768 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1014-ND - BOARD FOR LPC9XX TSSOP 622-1011-ND - BOARD FOR LPC938 TSSOP 622-1008-ND - BOARD FOR LPC9103 10-HVSON 622-1006-ND - SOCKET ADAPTER BOARD 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART 568-3510-ND - DEMO BOARD SPI/I2C TO UART 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X 568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY |
| 其它名稱： | 568-2013-5 935278546529 P89LPC938FDH-S |
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9397 750 14051
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 25 February 2005
9 of 68
Philips Semiconductors
P89LPC938
8-bit microcontroller with 10-bit A/D converter
P1.3/INT0/SDA
11
7
I/O
P1.3 — Port 1 bit 3 (open-drain when used as output).
I
INT0 — External interrupt 0 input.
I/O
SDA — I2C serial data input/output.
P1.4/INT1
10
6
I
P1.4 — Port 1 bit 4.
I
INT1 — External interrupt 1 input.
P1.5/RST
6
2
I
P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input during power-on or if selected via UCFG1.
When functioning as a reset input, a LOW on this pin resets the
microcontroller, causing I/O ports and peripherals to take on their default
states, and the processor begins execution at address 0. Also used
during a power-on sequence to force In-System Programming mode.
When using an oscillator frequency above 12 MHz, the reset input
function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its
specied level. When system power is removed VDD will fall below
the minimum specied operating voltage. When using an oscillator
frequency above 12 MHz, in some applications, an external
brownout detect circuit may be required to hold the device in reset
when VDD falls below the minimum specied operating range.
P1.6/OCB
5
1
I/O
P1.6 — Port 1 bit 6.
O
OCB — Output Compare B.
P1.7/OCC/
AD04
4
28
I/O
P1.7 — Port 1 bit 7.
O
OCC — Output Compare C.
I
AD04 — ADC0 channel 4 analog input.
P2.0 to P2.7
I/O
Port 2: Port 2 is an 8-bit I/O port with a user-congurable output type.
During reset Port 2 latches are congured in the input only mode with the
internal pull-up disabled. The operation of Port 2 pins as inputs and
outputs depends upon the port conguration selected. Each port pin is
congured independently. Refer to Section 7.13.1 “Port congurations”
and Table 10 “DC electrical characteristics” for details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described below:
P2.0/ICB/AD07
1
25
I/O
P2.0 — Port 2 bit 0.
I
ICB — Input Capture B.
I
AD07 — ADC0 channel 7 analog input.
P2.1/OCD/
AD06
2
26
I/O
P2.1 — Port 2 bit 1.
O
OCD — Output Compare D.
I
AD06 — ADC0 channel 6 analog input.
P2.2/MOSI
13
9
I/O
P2.2 — Port 2 bit 2.
I/O
MOSI — SPI master out slave in. When congured as master, this pin is
output; when congured as slave, this pin is input.
P2.3/MISO
14
10
I/O
P2.3 — Port 2 bit 3.
I/O
MISO — When congured as master, this pin is input, when congured
as slave, this pin is output.
Table 3:
Pin description …continued
Symbol
Pin
Type Description
TSSOP28,
PLCC28
HVQFN28
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