參數(shù)資料
型號: P89LPC938FDH,529
廠商: NXP Semiconductors
文件頁數(shù): 54/68頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 28-TSSOP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 51
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LED,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1011-ND - BOARD FOR LPC938 TSSOP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱: 568-2013-5
935278546529
P89LPC938FDH-S
PIC18F87J90 FAMILY
DS39933D-page 58
2010 Microchip Technology Inc.
5.7
Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 5-1.
These bits are used in software to determine the nature
of the Reset.
Table 5-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets, and WDT wake-ups.
TABLE 5-1:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition
Program
Counter(1)
RCON Register
STKPTR Register
RI
TO
PD
POR
BOR
STKFUL
STKUNF
Power-on Reset
0000h
111
00
0
RESET
Instruction
0000h
0uu
uu
u
Brown-out Reset
0000h
111
u0
u
MCLR during power-managed
Run modes
0000h
u1u
uu
u
MCLR during power-managed
Idle modes and Sleep mode
0000h
u10
uu
u
WDT time-out during full power
or power-managed Run modes
0000h
u0u
uu
u
MCLR during full-power
execution
0000h
uuu
uu
u
Stack Full Reset (STVREN = 1)
0000h
uuu
uu
1
u
Stack Underflow Reset
(STVREN = 1)
0000h
uuu
uu
u
1
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
uuu
uu
u
1
WDT time-out during
power-managed Idle or Sleep
modes
PC + 2
u00
uu
u
Interrupt exit from
power-managed modes
PC + 2
uu0
uu
u
Legend: u = unchanged
Note 1:
When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
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