參數(shù)資料
型號(hào): P89LPC938FDH,529
廠商: NXP Semiconductors
文件頁(yè)數(shù): 30/68頁(yè)
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 28-TSSOP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 51
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LED,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 706 (CN2011-ZH PDF)
配用: 622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1011-ND - BOARD FOR LPC938 TSSOP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱: 568-2013-5
935278546529
P89LPC938FDH-S
PIC18F87J90 FAMILY
DS39933D-page 36
2010 Microchip Technology Inc.
3.2
Control Registers
The OSCCON register (Register 3-1) controls the main
aspects of the device clock’s operation. It selects the
oscillator type to be used, which of the power-managed
modes to invoke and the output frequency of the
INTOSC source. It also provides status on the oscillators.
The OSCTUNE register (Register 3-2) controls the
tuning and operation of the internal oscillator block. It
also implements the PLLEN bits which control the
operation of the Phase Locked Loop (PLL) (see
REGISTER 3-1:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0
R/W-1
R/W-0
R(1)
R-0
R/W-0
IDLEN
IRCF2(2)
IRCF1(2)
IRCF0(2)
OSTS
IOFS
SCS1(4)
SCS0(4)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IDLEN: Idle Enable bit
1
= Device enters an Idle mode when a SLEEP instruction is executed
0
= Device enters Sleep mode when a SLEEP instruction is executed
bit 6-4
IRCF<2:0>: INTOSC Source Frequency Select bits(2)
111
= 8 MHz (INTOSC drives clock directly)
110
= 4 MHz (default)
101
= 2 MHz
100
= 1 MHz
011
= 500 kHz
010
= 250 kHz
001
= 125 kHz
000
= 31 kHz (from either INTOSC/256 or INTRC)(3)
bit 3
OSTS: Oscillator Start-up Timer Time-out Status bit(1)
1
= Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running
0
= Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready
bit 2
IOFS: INTOSC Frequency Stable bit
1
= Fast RC oscillator frequency is stable
0
= Fast RC oscillator frequency is not stable
bit 1-0
SCS<1:0>: System Clock Select bits(4)
11
= Internal oscillator block
10
= Primary oscillator
01
= Timer1 oscillator
00
= Default primary oscillator (as defined by the FOSC<2:0> Configuration bits)
Note 1:
Reset state depends on the state of the IESO Configuration bit.
2:
Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
3:
Source selected by the INTSRC bit (OSCTUNE<7>), see text.
4:
Modifying these bits will cause an immediate clock source switch.
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