參數(shù)資料
型號(hào)： P89LPC982FDH,529
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 33/85頁(yè)
文件大?。?/td> 0K
描述： MCU 80C51 8KB FLASH 28TSSOP
標(biāo)準(zhǔn)包裝： 51
系列： LPC900
核心處理器： 8051
芯體尺寸： 8-位
速度： 18MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 26
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
包裝： 管件
其它名稱： 568-8751-5
P89LPC982FDH,529-ND
P89LPC980_982_983_985
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 15 June 2010
39 of 85
NXP Semiconductors
P89LPC980/982/983/985
8-bit microcontroller with accelerated two-clock 80C51 core
7.16 I/O ports
The P89LPC980/982/983/985 has four I/O ports: Port 0, Port 1, Port 2 and Port 3. Ports 0,
1, and 2 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available
depends upon the clock and reset options chosen, as shown in Table 9.
7.16.1 Port configurations
All but three I/O port pins on the P89LPC980/982/983/985 may be configured by software
to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51
port outputs), push-pull, open drain, and input-only. Two configuration registers for each
port select the output type for each port pin.
1. P1.5 (RST) can only be an input and cannot be configured.
2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or
open-drain.
7.16.1.1
Quasi-bidirectional output configuration
Quasi-bidirectional output type can be used as both an input and output without the need
to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similar to an open-drain output except that there are three pull-up transistors in
the quasi-bidirectional output that serve different purposes.
A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
7.16.1.2
Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output, a port configured in this manner must have an external pull-up, typically a resistor
tied to VDD.
An open-drain port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
Table 9.
Number of I/O pins available
Clock source
Reset option
Number of I/O
pins (28-pin
package)
On-chip oscillator or watchdog
oscillator
No external reset (except during
power-up)
26
External RST pin supported
25
External clock input
No external reset (except during
power-up)
25
External RST pin supported
24
Low/medium/high speed
oscillator (external crystal or
resonator)
No external reset (except during
power-up)
24
External RST pin supported
23
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