參數(shù)資料
型號(hào): P89LPC982FDH,529
廠商: NXP Semiconductors
文件頁(yè)數(shù): 36/85頁(yè)
文件大小: 0K
描述: MCU 80C51 8KB FLASH 28TSSOP
標(biāo)準(zhǔn)包裝: 51
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 管件
其它名稱: 568-8751-5
P89LPC982FDH,529-ND
P89LPC980_982_983_985
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 15 June 2010
41 of 85
NXP Semiconductors
P89LPC980/982/983/985
8-bit microcontroller with accelerated two-clock 80C51 core
Please refer to P89LPC980/982/983/985 User manual for detail configurations.
7.17 Power management
The P89LPC980/982/983/985 support a variety of power management features.
Power-on detect and brownout detect are designed to prevent incorrect operation during
initial power-up and power loss or reduction during operation.
The P89LPC980/982/983/985 support three different power reduction modes: Idle mode,
Power-down mode, and total Power-down mode. In addition, individual on-chip
peripherals can be disabled to eliminate unnecessary dynamic power use in any
peripherals that are not required for the application.
Integrated PMU automatically adjusts internal regulators to minimize power consumption
during Idle mode, Power-down mode and total Power-down mode. In addition, the power
consumption can be further reduced in Normal or Idle mode through configuring
regulators mode according to the applications.
7.17.1 Brownout detection
The brownout detect function determines if the power supply voltage drops below a
certain level. Enhanced brownout detection has 3 independent functions: BOD reset,
BOD interrupt and BOD flash.
These three functions are disabled in Power-down mode and Total Power-down mode. In
Normal or Idle mode, BOD reset and BOD flash are always on and can not be disabled in
software. BOD interrupt may be enabled or disabled in software.
BOD reset and BOD interrupt, each has 6 levels. BOE0 to BOE2 (UCFG1[3:5]) are used
as trip point configuration bits of BOD reset. BOICFG0 to BOICFG2 in register BODCFG
are used as trip point configuration bits of BOD interrupt.
BOD reset voltage should be lower than BOD interrupt trip point. BOD flash is used for
flash programming/erase protection and has only 1 trip point at 2.4 V. Please refer to
P89LPC980/982/983/985 User manual for detail configurations.
If brownout detection works, the brownout condition occurs when VDD falls below the
brownout falling trip voltage and is negated when VDD rises above the brownout rising trip
voltage.
Table 10.
SPI/I2C/UART pin remap
Peripherals
Function
Primary pin out
Alternative pin out
SPI
SPICLK
P2.5
P0.0
MOSI
P2.2
P1.7
MISO
P2.3
P1.6
SS
P2.4
P1.4
I2C
SDA
P1.3
P2.7
SCL
P1.2
P2.6
UART
TXD
P1.0
P2.0
RXD
P1.1
P2.1
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