參數(shù)資料
型號(hào)： P89LPC982FDH,529
廠商： NXP Semiconductors
文件頁數(shù)： 4/85頁
文件大?。?/td> 0K
描述： MCU 80C51 8KB FLASH 28TSSOP
標(biāo)準(zhǔn)包裝： 51
系列： LPC900
核心處理器： 8051
芯體尺寸： 8-位
速度： 18MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 26
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
包裝： 管件
其它名稱： 568-8751-5
P89LPC982FDH,529-ND
P89LPC980_982_983_985
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 15 June 2010
12 of 85
NXP Semiconductors
P89LPC980/982/983/985
8-bit microcontroller with accelerated two-clock 80C51 core
P1.7/AD04/T3EX/
MOSI
4I/O
P1.7 — Port 1 bit 7. High current source.
I
AD04 — ADC0 channel 4 analog input. (P89LPC985)
I
T3EX — Timer/counter 3 external capture input.
I/O
MOSI — SPI master out slave in. When configured as master, this pin is output;
when configured as slave, this pin is input. (pin remap)
P2.0 to P2.7
I/O
Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset
Port 2 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 2 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to Section
All pins have Schmitt trigger inputs.
Port 2 also provides various special functions as described below:
P2.0/AD07/TXD
1
I/O
P2.0 — Port 2 bit 0.
I
AD07 — ADC0 channel 7 analog input. (P89LPC985)
O
TXD — Transmitter output for serial port. (pin remap)
P2.1/AD06/RXD
2
I/O
P2.1 — Port 2 bit 1.
I
AD06 — ADC0 channel 6 analog input. (P89LPC985)
I
RXD — Receiver input for serial port. (pin remap)
P2.2/MOSI
13
I/O
P2.2 — Port 2 bit 2.
I/O
MOSI — SPI master out slave in. When configured as master, this pin is output;
when configured as slave, this pin is input.
P2.3/MISO
14
I/O
P2.3 — Port 2 bit 3.
I/O
MISO — SPI master in slave out. When configured as master, this pin is input,
when configured as slave, this pin is output.
P2.4/SS
15
I/O
P2.4 — Port 2 bit 4.
I
SS — SPI Slave select.
P2.5/SPICLK
16
I/O
P2.5 — Port 2 bit 5.
I/O
SPICLK — SPI clock. When configured as master, this pin is output; when
configured as slave, this pin is input.
P2.6/SCL
27
I/O
P2.6 — Port 2 bit 6.
I/O
SCL — I2C-bus serial clock input/output. (pin remap)
P2.7/SDA
28
I/O
P2.7 — Port 2 bit 7.
I/O
SDA — I2C-bus serial data input/output. (pin remap)
P3.0 to P3.1
I/O
Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset
Port 3 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 3 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to Section
All pins have Schmitt trigger inputs.
Port 3 also provides various special functions as described below:
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
PLCC28,
TSSOP28
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