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參數(shù)資料
| 型號： | P89V51RB2BBC,557 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 42/80頁 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU 1024 RAM 44TQFP |
| 產(chǎn)品培訓模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標準包裝： | 800 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 16KB（16K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
| 配用： | 622-1017-ND - BOARD 44-ZIF PLCC SOCKET |
| 其它名稱： | 935277723557 P89V51RB2BBC P89V51RB2BBC-ND |
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P89V51RB2_RC2_RD2_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 November 2009
47 of 80
NXP Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
In the CMOD SFR there are three additional bits associated with the PCA. They are CIDL
which allows the PCA to stop during Idle mode, WDTE which enables or disables the
Watchdog function on module 4, and ECF which when set causes an interrupt and the
PCA overow ag CF (in the CCON SFR) to be set when the PCA timer overows.
The watchdog timer function is implemented in module 4 of PCA.
The CCON SFR contains the run control bit for the PCA (CR) and the ags for the PCA
timer (CF) and each module (CCF4:0). To run the PCA the CR bit (CCON.6) must be set
by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the
PCA counter overows and an interrupt will be generated if the ECF bit in the CMOD
register is set. The CF bit can only be cleared by software. Bits 0 through 4 of the CCON
register are the ags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are
set by hardware when either a match or a capture occurs. These ags can only be cleared
by software. All the modules share one interrupt vector. The PCA interrupt system is
shown in Figure 22.
Each module in the PCA has a special function register associated with it. These registers
are: CCAPM0 for module 0, CCAPM1 for module 1, etc. The registers contain the bits that
control the mode that each module will operate in.
The ECCF bit (from CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module)
enables the CCFn ag in the CCON SFR to generate an interrupt when a match or
compare occurs in the associated module (see Figure 22).
PWM (CCAPMn.1) enables the pulse width modulation mode.
The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to
toggle when there is a match between the PCA counter and the module’s
capture/compare register.
The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to
be set when there is a match between the PCA counter and the module’s
capture/compare register.
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a
capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit
enables the positive edge. If both bits are set both edges will be enabled and a capture will
occur for either transition.
The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
There are two additional registers associated with each of the PCA modules. They are
CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a
capture occurs or a compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output.
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