參數(shù)資料
型號(hào): P89V51RB2BBC,557
廠商: NXP Semiconductors
文件頁數(shù): 60/80頁
文件大小: 0K
描述: IC 80C51 MCU 1024 RAM 44TQFP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 800
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 44-TQFP
包裝: 托盤
配用: 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
其它名稱: 935277723557
P89V51RB2BBC
P89V51RB2BBC-ND
2009-2011 Microchip Technology Inc.
DS39960D-page 63
PIC18F87K22 FAMILY
4.4.1
PRI_IDLE MODE
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing-sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate, primary clock source, since the clock source
does not have to “warm-up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC<3:0> Configuration bits. The OSTS bit
remains set (see Figure 4-7).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval, TCSD
(Parameter 39, Table 31-13), is required between the
wake event and the start of code execution. This is
required to allow the CPU to become ready to execute
instructions. After the wake-up, the OSTS bit remains
set. The IDLEN and SCS bits are not affected by the
wake-up (see Figure 4-8).
4.4.2
SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the SOSC
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS<1:0> bits to ‘01’ and execute
SLEEP
. When the clock source is switched to the SOSC
oscillator, the primary oscillator is shut down, the OSTS
bit is cleared and the SOSCRUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the SOSC oscillator. After an interval
of TCSD following the wake event, the CPU begins
executing code being clocked by the SOSC oscillator.
The IDLEN and SCS bits are not affected by the wake-
up and the SOSC oscillator continues to run (see
FIGURE 4-7:
TRANSITION TIMING FOR ENTRY TO IDLE MODE
FIGURE 4-8:
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1
Peripheral
Program
PC
PC + 2
OSC1
Q3
Q4
Q1
CPU Clock
Clock
Counter
Q2
OSC1
Peripheral
Program
PC
CPU Clock
Q1
Q3
Q4
Clock
Counter
Q2
Wake Event
TCSD
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