參數(shù)資料
型號: PC56F8006VLF
廠商: Freescale Semiconductor
文件頁數(shù): 41/106頁
文件大?。?/td> 0K
描述: DSP 16BIT 48-LQFP
標準包裝: 250
系列: 56F8xxx
核心處理器: 56800
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
RAM 容量: 1K x 16
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 24x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 托盤
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Block Diagram
Freescale Semiconductor
4
2
Block Diagram
Figure 1 shows a top-level block diagram of the MC56F8006/MC56F8002 digital signal controller. Package options for this
family are described later in this document. Italics indicate a 56F8002 device parameter.
Figure 1. MC56F8006/MC56F8002 Block Diagram
3
Overview
3.1
56F8006/56F8002 Features
3.1.1
Core
Efficient 16-bit 56800E family digital signal controller (DSC) engine with dual Harvard architecture
As many as 32 million instructions per second (MIPS) at 32 MHz core frequency
155 basic instructions in conjunction with up to 20 address modes
Single-cycle 16
16-bit parallel multiplier-accumulator (MAC)
Four 36-bit accumulators, including extension bits
32-bit arithmetic and logic multi-bit shifter
Program Controller
and Hardware
Looping Unit
Data ALU 16 x 16 + 36
36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Address
Generation Unit
Bit
Manipulation
Unit
16-Bit 56800E Core
Interrupt
Controller
4
Unified Data /
Program RAM
2KB
PDB
CDBR
SPI
IPBus Bridge
R/W Control
Memory
PAB
CDBW
JTAG/EOnCE
Port or GPIOD
Digital Reg
Analog Reg
Low-Voltage
Supervisor
VDD
VSS
VDDA VSSA
4
RESET
6
Dual GP Timer
ADCA
4
24 Total
Clock
Generator*
System
Integration
Module
ROSC
PWM Outputs
PWM
COP/
Watchdog
ADCB
Flash Memory
16 Kbytes flash
12 Kbytes flash
PGA/ADC
SCI
2
3
CMP0
2
CMP2
2
CMP
or
GPIOD
CMP1
2
Crystal
Oscillator
Power
Management
Controller
programmable
I2C
2
PIT
delay block
3
40
GPIO are
muxed with
all other func
pins.
PMC
3
Fault Inputs
PDB
XAB1
XAB2
System Bus
Control
PAB
CDBR
CDBW
XDB2
OSC
RTC
Note: All pins
are muxed with
other peripheral
pins.
2
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