參數(shù)資料
型號: PC56F8006VLF
廠商: Freescale Semiconductor
文件頁數(shù): 91/106頁
文件大?。?/td> 0K
描述: DSP 16BIT 48-LQFP
標(biāo)準(zhǔn)包裝: 250
系列: 56F8xxx
核心處理器: 56800
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
RAM 容量: 1K x 16
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 24x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 托盤
Interrupt Vector Table
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
85
Reserved
34- 39
0x22-0x27
0
P:0x44 -
P:0x4E
Reserved
core
40
N/A
0
P:0x50
SW Interrupt 0
core
41
N/A
1
P:0x52
SW Interrupt 1
core
42
N/A
2
P:0x54
SW Interrupt 2
core
43
N/A
3
P:0x56
SW Interrupt 3
SWILP
44
N/A
-1
P:0x58
SW Interrupt Low Priority
USER1
45
N/A
1
P:0x5A
User Programmable Priority Level 1 Interrupt
USER2
46
N/A
1
P:0x5C
User Programmable Priority Level 1 Interrupt
USER3
47
N/A
1
P:0x5E
User Programmable Priority Level 1 Interrupt
USER4
48
N/A
2
P:0x60
User Programmable Priority Level 2 Interrupt
USER5
49
N/A
2
P:0x62
User Programmable Priority Level 2 Interrupt
USER6 3
50
N/A
2
P:0x64
User Programmable Priority Level 2 Interrupt
1 Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from
the vector table, providing only 19 bits of address.
2 If the VBA is set to the reset value, the first two locations of the vector table overlay the chip reset addresses because the
reset address would match the base of this vector table.
3 USER6 vector can be defined as a fast interrupt if the instruction located in this vector location is not a JSR or BSR instruction.
Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference Manual for detail.
Table 43. Interrupt Vector Table Contents1 (continued)
Peripheral
Vector
Number
User
Encoding
Priority
Level
Vector Base
Address +
Interrupt Function
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