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| 型號： | PC755BVZFU300LD |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|PLASTIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 360PIN |塑料 |
| 文件頁數(shù)： | 25/48頁 |
| 文件大?。?/td> | 276K |
| 代理商： | PC755BVZFU300LD |
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PC755B/745B
25/48
4.2. Dynamic characteristics
After fabrication, parts are sorted by maximum processor core frequency as shown in Section 4.2.1.,“Clock AC Specifications” and
tested for conformance to the AC specifications for that frequency. These specifications are for 275, 300, 333 MHz processor core
frequencies. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0–3]
signals. Parts are sold by maximum processor core frequency.
4.2.1. Clock AC Specifications
Table 10 provides the clock AC timing specifications as defined in Table 3.
Table 10. Clock AC Timing Specifications
At recommended operating conditions (See Table 5)
Characteristic
Symbol
Maximum Processor Core Frequency
Unit
Notes
300 MHz
350 MHz
400 MHz
Min
Max
Min
Max
Min
Max
Processor frequency
f
core
200
300
200
350
200
400
MHz
1
VCO frequency
f
VCO
400
600
400
700
400
800
MHz
1
SYSCLK frequency
f
SYSCLK
25
100
25
100
25
100
MHz
1
SYSCLK cycle time
t
SYSCLK
10
40
10
40
10
40
ns
SYSCLK rise and fall time
t
KR
&
t
KF
—
2.0
—
2.0
—
2.0
ns
2
t
KR
&
t
KF
—
1.0
—
1.0
—
1.0
ns
2
SYSCLK duty cycle
measured at OVdd/2
t
KHKL
/t
SYSC
LK
40
60
40
60
40
60
%
3
SYSCLK jitter
—
150
—
150
—
150
ps
3,4
Internal PLL relock time
—
100
—
100
—
100
μ
s
3,5
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to the PLL_CFG[0–3] signal description in Table 17,” for valid PLL_CFG[0–3] settings
2. Rise and fall times measurements are now specified in terms of slew rates, rather than time to account for selectable
I/O bus interface levels. The minimum slew rate of 1v/ns is equivalent to a 2ns maximum rise/fall time measured at
0.4v and 2.4v or a rise/fall time of 1ns measured at 0.4v to 1.4v.
3. Timing is guaranteed by design and characterization.
4. This represents total input jitter - short term and long term combined and is guaranteed by design.
5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time
required for PLL lock after a stable Vdd and SYSCLK are reached during the power-on reset sequence. This specifi-
cation also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note
that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on
reset sequence.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC755BVZFU350LD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|PLASTIC |
| PC755BVZFU400LD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|PLASTIC |
| PC755CMGHU300LE | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 755/745 RISC Microprocessor |
| PC755CMGHU350LE | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 755/745 RISC Microprocessor |
| PC755CMGHU366LE | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 755/745 RISC Microprocessor |
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