PC755B/745B
35/48
Figure 22 provides the test access port timing diagram.
TCK
TDI, TMS
TDO
VM = Midpoint Voltage (OVDD/2)
TDO
VM
VM
tIXJH
tIVJH
tJLOV
tJLOH
tJLOZ
INPUT
DATA VALID
DATA
VALID
OUTPUT DATA VALID
Figure 22 : Test Access Port Timing Diagram
4.2.5.2. JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification
but is provided on all PowerPC implementations. While it is possible to force the TAP controller to the reset state using only the TCK
and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.
Since the JTAG interface is also used for accessing the common on-chip processor (COP) function of PowerPC processors, simply
tying TRST to HRESET isn’t practical.
The common on-chip processor (COP) function of PowerPC processors allows a remote computer system (typically a PC with dedi-
cated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects
primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to
independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources,
such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be
merged into these signals with logic.
The arrangement shown in Figure 23 allows the COP to independently assert HRESET or TRST, while insuring that the target can
drive HRESET as well. The pull-down resistor on TRST ensures that the JTAG scan chain is initialized during power-on if a JTAG
interface cable is not attached; if it is, it is responsible for driving TRST when needed.
Figure 23 shows the suggested TRST connection.
HRESET
HRESET
TRST
From Target
Board
Sources
COP Header
2KW
QACK
QACK
2KW
PC755B
Figure 23 : Suggested TRST Connection