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參數(shù)資料
| 型號(hào)： | PC755BVZFU300LD |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|PLASTIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 360PIN |塑料 |
| 文件頁數(shù)： | 26/48頁 |
| 文件大小： | 276K |
| 代理商： | PC755BVZFU300LD |
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PC755B/745B
Figure 10 provides the SYSCLK input timing diagram.
SYSCLK
VM
VM
VM
KVIH
KVIL
VM = Midpoint Voltage (OVDD/2)
tSYSCLK
tKR
tKF
tKHKL
Figure 10 : SYSCLK Input Timing Diagram
4.2.2. Processor Bus AC Specifications
Table 11 provides the processor bus AC timing specifications for the PC755B as defined in Figure 11 and Figure 13 . Timing specifi-
cations for the L2 bus are provided in Section 4.2.1., “ L2 Clock AC Specifications.
Table 11. Processor Bus Mode Selection AC Timing Specifications
1
At Vdd=AVdd=2.0V 100mV; -55
Tj
+125
o
C, OVdd = 3.3V
165mV and OVdd = 1.8V
100mV and OVdd = 2.0V100mV
Parameter
Symbols
2
300, 350, 400 MHz
Unit
Notes
Min
Max
Mode select input setup to HRESET
t
MVRH
8
—
t
sysclk
3,4,5,6,7
HRESET to mode select input hold
t
MXRH
∞
—
ns
3,4,6,7,8
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of
the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the mid-
point of the signal in question. All output timings assume a purely resistive 50 ohm load (See Figure 11). Input and
output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors
in the system.
2. he symbology used for timing specifications herein follows the pattern of t
(signal)(state)(reference)(state)
for inputs and
t
(reference)(state)(signal)(state)
for outputs. For example, t
IVKH
symbolizes the time input signals (I) reach the valid state
(V) relative to the SYSCLK reference (K) going to the high(H) state or input setup time. And t
KHOV
symbolizes the time
from SYSCLK(K) going high(H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the
time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) - note the position of the reference
and its state for inputs -and output hold time can be read as the time from the rising edge (KH) until the output went
invalid (OX). For additional explanation of AC timing specifications in Motorola PowerPC microprocessors, see the
application note “Understanding AC Timing Specifications for PowerPC Microprocessors.”
3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 11).
4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a mini-
mum of 255 bus clocks after the PLL re-lock time during the power-on reset sequence.
5. t
sysclk
is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multi-
plied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
6. Mode select signals are BVSEL, L2VSEL, PLL_CFG[0-3]
7. Guaranteed by design and characterization.
8. Bus mode select pins must remain stable during operation. Changing the logic states of BVSEL or L2VSEL during
operation will cause the bus mode voltage selection to change. Changing the logic states of the PLL_CFG pins during
operation will cause the PLL division ratio selection to change. Both of these conditions are considered outside the
specification and are not supported. Once HRESET is negated the states of the bus mode selection pins must remain
stable.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC755BVZFU350LD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|PLASTIC |
| PC755BVZFU400LD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|PLASTIC |
| PC755CMGHU300LE | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 755/745 RISC Microprocessor |
| PC755CMGHU350LE | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 755/745 RISC Microprocessor |
| PC755CMGHU366LE | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PowerPC 755/745 RISC Microprocessor |
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