參數(shù)資料
型號(hào)： PC755CVGSU366LE
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： PowerPC 755/745 RISC Microprocessor
中文描述： 32-BIT, 366 MHz, RISC PROCESSOR, CBGA360
封裝： SOLDER COLUMN INTERPOSER, CERAMIC, BGA-360
文件頁(yè)數(shù)： 27/50頁(yè)
文件大?。?/td> 1064K
代理商： PC755CVGSU366LE
27
PC755/745
2138D–HIREL–06/03
Figure 12 provides the AC test load for the PC755.
Figure 12.
AC Test Load
Notes:
1. Revisions prior to Rev 2.8 (Rev E) were limited in performance and did not conform to this specification. Contact your local
Motorola sales office for more information.
2. Guaranteed by design and characterization.
3. t
SYSCLK
is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied
by the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. Per the 60x bus protocol, TS, ABB and DBB are driven only by the currently active bus master. They are asserted low then
precharged high before returning to high-Z as shown in Figure 6. The nominal precharge width for TS, ABB or DBB is 0.5 x
t
, i.e. less than the minimum t
period, to ensure that another master asserting TS, ABB, or DBB on the following
clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid
time is tested for precharge.The high-Z behavior is guaranteed by design.
5. Per the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following
AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it low. Any master asserting it low in
the first clock following AACK will then go to high-Z for one clock before precharging it high during the second cycle after the
assertion of AACK. The nominal precharge width for ARTRY is 1.0 t
; i.e., it should be high-Z as shown in Figure 6
before the first opportunity for another master to assert ARTRY. Output valid and output hold timing is tested for the signal
asserted. Output valid time is tested for precharge. The high-Z and precharge behavior is guaranteed by design.
OVDD/2
OUTPUT
Z0 = 50
R
L
= 50
Table 14.
Processor Bus AC Timing Specifications
(1)
at Recommended Operating Conditions
Parameter
Symbols
All Speed Grades
Unit
Min
Max
Setup Times: All Inputs
t
IVKH
2.5
–
ns
Input Hold Times:
TLBISYNC
,
MCP
,
SMI
t
IXKH
0.6
–
ns
Input Hold Times: All Inputs, except
TLBISYNC
,
MCP
,
SMI
t
IXKH
0.2
–
ns
Valid Times: All Outputs
t
KHOV
–
4.1
ns
Output Hold Times: All Outputs
t
KHOX
1
–
ns
SYSCLK to Output Enable
(2)
t
KHOE
0.5
–
ns
SYSCLK to Output High Impedance (all except
ABB
,
ARTRY
,
DBB
)
(2)
t
KHOZ
–
6
ns
SYSCLK to
ABB
,
DBB
High Impedance After Precharge
(2)(3)(4)
t
KHABPZ
–
1
t
SYSCLK
Maximum Delay to
ARTRY
Precharge
(2)(3)(5)
t
KHARP
–
1
t
SYSCLK
SYSCLK to
ARTRY
High Impedance After Precharge
(2)(3)(5)
t
KHARPZ
–
2
t
SYSCLK
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