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參數(shù)資料
| 型號： | PCD6001U |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Digital telephone answering machine chip |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, UUC |
| 文件頁數(shù)： | 37/96頁 |
| 文件大?。?/td> | 385K |
| 代理商： | PCD6001U |
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2001 Apr 17
37
Philips Semiconductors
Product specification
Digital telephone answering machine chip
PCD6001
10.11 I
2
C-bus
The serial port I
2
C-bus is a simple bidirectional 2-wire bus
for efficient inter IC data exchange. The I
2
C-bus consists
of a data line (SDA) and a clock line (SCL). These lines
also function as I/O Port P1.7 and P1.6 respectively.
The system is unique because data transport, clock
generation, address recognition and bus arbitration are all
controlled by hardware. The I
2
C-bus serial I/O has
complete autonomy in byte handling and supports all four
I
2
C-bus operating modes:
Master transmitter
Master receiver
Slave transmitter
Slave receiver.
The I
2
C-bus block contains 4 SFR registers. The mode of
operation is controlled by the S1CON register. S1STA is
the status register whose contents may also be used as a
vector to various service routines. S1DAT is the data shift
register and S1ADR is the slave address register. Slave
address recognition is performed by hardware.
An application note is available to help implementation of
the software for the I
2
C-bus.
handbook, full pagewidth
MGM777
S1ADR
DATA SHIFT REGISTER
S1DAT
SDA
BUS ARBITRATION LOGIC
SCL
BUS CLOCK GENERATOR
M
S1CON
SERIAL CONTROL REGISTER
STATUS REGISTER
OWN ADDRESS REGISTER
S1STA
Fig.13 I
2
C-bus serial I/O.
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