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參數(shù)資料
| 型號(hào)： | PCD6001U |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Digital telephone answering machine chip |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, UUC |
| 文件頁數(shù)： | 66/96頁 |
| 文件大小： | 385K |
| 代理商： | PCD6001U |
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2001 Apr 17
66
Philips Semiconductors
Product specification
Digital telephone answering machine chip
PCD6001
15 IOM
15.1
Features
The IOM block in the PCD6001 is a 4-wire serial interface
performing following functions:
Digital interface with up to two 64 kbits/s channels at a
bit rate of n
×
256 kbits/s (n = 1, 2, 3, 4 or 8), complying
with the “IOM-2 specifications”(IOM-2 is a registered
trademark of Siemens AG)
Digital interface with 32 slots/frame and non-doubled
data clock; compatible with the digital interface of some
speech CODEC ICs
Autonomous storing/fetching of data into/from the
DSP I/O registers
Byte or word (16 bits) transfer.
15.2
Pin description
The following pins are used by the IOM interface:
DI: serial data input with a bit rate of n
×
256 kbits/s
(n = 1, 2, 3, 4 or 8)
DO: serial data output with a bit rate of n
×
256 kbits/s
(n = 1, 2, 3, 4 or 8)
FSC: 8 kHz frame synchronization input/output
DCK: data clock input/output. Twice the data
transmission frequency on DI and DO, except in the
non-doubled data clock mode (see Section 15.3).
These pins are alternative functions of P3. When
activated, DO is an open-drain pin, as many devices must
be able to write on the same data line in a time-multiplexed
mode. Therefore DO must be externally pulled-up. FSC
andDCKareinputsorpush-pulloutputs,dependingonthe
IOM being in Slave or Master mode. Activation of the IOM
alternative functions of P3 and switching between Slaveor
Master mode is controlled by the SFR ALTP, bit 6 and 5
respectively (see Section 16.2 for more details).
15.3
Functional description
The digital interface of the PCD6001 can work at several
bit rates, summarized in Table 61. A particular bit rate is
selected by writing the 3-bit code given in the first column
of the table into the IOM control register bits IOMC[15:13].
Choosing the code ‘000’ or ‘001’ deactivates the IOM
interface and stops all the transactions on the IOM bus.
This is the default state after reset.
The PCD6001 IOM can be master or slave. After reset the
IOM is in Slave mode. Switching between Slave or Master
mode is controlled by the SFR ALTP, bit 6 and bit 5
respectively (see Section 16.2.5 for more details). In Slave
mode both FSC and DCK are inputs. In Master mode both
FSC and DCK are outputs. In Master mode FSC and DCK
aregeneratedbytheTICB(seeSection 9.1).Mastermode
should only be used in combination with the bit rate
768 kbits/s. Slave mode should only be used when
operating with a 3.456 MHz (or multiple) crystal. In
general, proper IOM functionality is only guaranteed
at DSP operating frequencies of 28 and 42 MHz.
FSC is an 8 kHz framing signal for synchronizing data
transmission on DI and DO. The rising edge of FSC gives
the time reference for the first bit transmitted in the first slot
of a speech frame. The number of slots per speech frame
depends on the selected data rate. Each slot contains
8 data bits.
DCK is a data clock. Its frequency is twice the selected
data rate in IOM mode. In speech mode, the
DCK frequency is equal to the data rate (2048 kHz for
2048 kbits/s).
DI is the serial data input. Data coming on DI in packets of
8 bits (A-law PCM encoded data) or 16 bits (linear PCM
data) is stored temporarily in an IOM data buffer, from
where it is processed by the on-chip DSP. On the other
hand, data written into the IOM data buffers by the DSP is
shifted out on pin DO.
There are two IOM data buffers, allowing the use of two
8-bit channel. One channel is 64 kbits/s in case of A-law
PCM encoded data and 128 kbits/s if linear PCM data is
transferred, in which case two consecutive slots are used.
The speech mode was implemented to support the Codec
interface of some speech compression ICs. This mode is
very similar to the IOM 32 slots mode, the main difference
being the non-doubled data clock. See Section 15.6 for
timing information.
15.4
IOM data buffers
Table 58 and 59 show the two 16-bit DSP registers used
as data buffers: IOMDI for storing inbound data and
IOMDO for the outbound data. The high bytes store the
data of buffer 1, the low bytes the data of buffer 0.
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