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參數(shù)資料
| 型號： | PCD6001U |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Digital telephone answering machine chip |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, UUC |
| 文件頁數(shù)： | 38/96頁 |
| 文件大?。?/td> | 385K |
| 代理商： | PCD6001U |
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2001 Apr 17
38
Philips Semiconductors
Product specification
Digital telephone answering machine chip
PCD6001
10.11.1 S
ERIAL
C
ONTROL
R
EGISTER
(S1CON)
Two bits are affected by the I
2
C-bus hardware, the SI bit is set to logic 1 when a serial interrupt is requested, and the
STO bit is set to logic 0 (cleared) when a STOP condition is present on the I
2
C-bus. The STO bit is also cleared when
ENS1 = 0. When the I
2
C-bus block is in the Master mode the serial clock frequency is determined by the clock rate bits
CR[2:0].
Table 33
Serial Control Register (SFR address D8H)
Table 34
Description of S1CON bits
7
6
5
4
3
2
1
0
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
BIT
SYMBOL
DESCRIPTION
7
CR2
Clock rate.
This bit along with bits CR1 and CR0 determines the serial clock frequency
when I
2
C-bus is in Master mode, see Table 35.
When this bit is set to logic 0 the I
2
C-bus is disabled, outputs SDA and SCL are in the
high-impedance state, and P1.6 and P1.7 function as open-drain ports. With this bit set
to logic 1 the I
2
C-bus is enabled. The P1.6 and P1.7 port latch must be set to logic 1.
Start flag.
When the STA bit is set to logic 1 in Slave mode, the I
2
C-bus hardware
checks the status of the I
2
C-bus and generates a START condition if the bus is free. If
STA is set to logic 1 while the I
2
C-bus is in Master mode, the I
2
C-bus transmits a
repeated START condition.
Stop flag.
With this bit set to logic 1 while in Master mode a STOP condition is
generated. When a STOP condition is detected on the bus, the I
2
C-bus hardware clears
the STO flag. In the Slave mode, the STO flag may also be set to logic 1 to recover from
an error condition. In this case no STOP condition is transmitted to the I
2
C-bus.
However, the I
2
C-bus hardware behaves as if a STOP condition has been received and
releases SDA and SCL. The I
2
C-bus then switches to the ‘not addressed’ receiver
mode. The STO flag is automatically cleared by hardware.
I
2
C-bus interrupt flag.
When this flag is set to logic 1, an acknowledge is returned (i.e.
an interrupt is generated) after any one of the following conditions:
A start condition is generated in Master mode
Own slave address received during AA = 1
General call address received while S1ADR[0] = 1and AA = 1
Data byte received or transmitted in Master mode (even if arbitration is lost)
Data byte received or transmitted as selected slave
Stop or start condition received as selected slave receiver or transmitter.
Assert Acknowledge.
When set to logic 1 an acknowledge will be returned during the
acknowledge clock pulse on SCL when:
Own slave address is received
General call address is received while S1ADR[0] = 1
Data byte is received while device is a selected slave.
With AA = 0 no acknowledge will be returned. Consequently, no interrupt is requested
when the ‘own slave address’ or general call address is received.
Clock rate.
These 2 bits along with the CR2 bit determine the serial clock frequency
when I
2
C-bus is in Master mode, see Table 35.
6
ENS1
5
STA
4
STO
3
SI
2
AA
1
0
CR1
CR0
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