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| 型號： | PCI4515GHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED |
| 中文描述： | 單插槽CardBus控制器，它集成 |
| 文件頁數(shù)： | 148/216頁 |
| 文件大小： | 1138K |
| 代理商： | PCI4515GHK |
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716
Table 719. PCI Miscellaneous Configuration Register Description (Continued)
BIT
1
FIELD NAME
DISABLE_
PCIGATE
TYPE
RW
DESCRIPTION
When bit 1 is set to 1, the internal PCI clock runs identically with the chip input. This is a test feature
only and must be cleared to 0 (all applications).
0
KEEP_PCLK
RW
When bit 0 is set to 1, the PCI clock is always kept running through the CLKRUN protocol. When this
bit is cleared, the PCI clock can be stopped using CLKRUN on MFUNC6.
This bit is cleared only by the assertion of GRST.
7.22 Link Enhancement Control Register
The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial
EEPROM, if present. After these bits are set to 1, their functionality is enabled only if bit 22 (aPhyEnhanceEnable)
in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. See Table 720 for a
complete description of the register contents.
Bit
Name
Type
Default
31
30
29
28
27
26
25
Link enhancement control
R
R
0
0
24
23
22
21
20
19
18
17
16
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
Name
Type
Default
15
14
13
12
11
10
9
Link enhancement control
R
RW
0
0
8
7
6
5
4
3
2
1
0
RW
0
R
0
RW
0
RW
1
R
0
RW
0
RW
0
R
0
R
0
R
0
R
0
R
0
RW
0
R
0
Register:
Offset:
Type:
Default:
Link enhancement control
F4h
Read/Write, Read-only
0000 1000h
Table 720. Link Enhancement Control Register Description
BIT
3116
15
FIELD NAME
RSVD
dis_at_pipeline
TYPE
R
RW
DESCRIPTION
Reserved. Bits 3116 return 0s when read.
Disable AT pipelining. When bit 15 is set to 1, out-of-order AT pipelining is disabled. The default value for
this bit is 0.
14
1312
RSVD
atx_thresh
R
Reserved. Bit 14 defaults to 0 and must remain 0 for normal operation of the OHCI core.
This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the
controller retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward operation.
00 = Threshold ~ 2K bytes resulting in a store-and-forward operation
01 = Threshold ~ 1.7K bytes (default)
10 = Threshold ~ 1K bytes
11 = Threshold ~ 512 bytes
These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7K-byte threshold
is optimal. Changing this value may increase or decrease the 1394 latency depending on the average
PCI bus latency.
Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds
or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than
the AT threshold, then the remaining data must be received before the AT FIFO is emptied; otherwise,
an underrun condition occurs, resulting in a packet error at the receiving node. As a result, the link then
commences a store-and-forward operation. It waits until it has the complete packet in the FIFO before
retransmitting it on the second attempt to ensure delivery.
An AT threshold of 2K results in a store-and-forward operation, which means that asynchronous data is
not transmitted until an end-of-packet token is received. Restated, setting the AT threshold to 2K results
in only complete packets being transmitted.
Note that this controller always uses a store-and-forward operation when the asynchronous transmit
retries register at OHCI offset 08h (see Section 8.3) is cleared.
These bits are cleared only by the assertion of GRST.
RW
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