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參數(shù)資料
| 型號： | PCI4515GHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED |
| 中文描述： | 單插槽CardBus控制器，它集成 |
| 文件頁數(shù)： | 56/216頁 |
| 文件大?。?/td> | 1138K |
| 代理商： | PCI4515GHK |
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318
3.8.1
1394 Power Management (Function 2)
The PCI4515 controller complies with
PCI Bus Power Management Interface Specification
. The controller supports
the D0 (uninitialized), D0 (active), D1, D2, and D3 power states as defined by the power-management definition in
the
1394 Open Host Controller Interface Specification
, Appendix A.4 and
PCI Bus Power Management Specification
.
PME is supported to provide notification of wake events. Per Section A.4.2, the 1394 OHCI sets PMCSR.PME_STS
in the D0 state due to unmasked interrupt events. In previous OHCI implementations, unmasked interrupt events
were interpreted as (IntEvent.n && IntMask.n && IntMask.masterIntEnable), where n represents a specific interrupt
event. Based on feedback from Microsoft this implementation may cause problems with the existing Windows
power-management arcitecture as a PME and an interrupt could be simultaneously signaled on a transition from the
D1 to D0 state where interrupts were enabled to generate wake events. If bit 10 (ignore_mstrIntEna_for_pme) in the
PCI miscellaneous configuration register (OHCI offset F0h, see Section 7.21) is set, then the PCI4515 controller
implements the preferred behavior as (IntEvent.n && IntMask.n). Otherwise, the PCI4515 controller implements the
preferred behavior as (IntEvent.n && IntMask.n && IntMask.masterIntEnable). In addition, when the
ignore_mstrIntEna_for_pme bit is set, it causes bit 26 of the OHCI vendor ID register (OHCI offset 40h, see
Section 8.15) to read 1, otherwise, bit 26 reads 0. An open drain buffer is used for PME. If PME is enabled in the power
management control/status register (PCI offset A4h, see Section 4.43), then insertion of a PC Card causes the
PCI4515 controller to assert PME, which wakes the system from a low power state (D3, D2, or D1). The OS services
PME and takes the PCI4515 controller to the D0 state.
3.8.2
Integrated Low-Dropout Voltage Regulator (LDO-VR)
The PCI4515 controller requires 1.5-V core voltage. The core power can be supplied by the PCI4515 controller itself
using the internal
LDO-VR. The core power can alternatively be supplied by an external power supply through the
VR_PORT terminal. Table 314 lists the requirements for both the internal core power supply and the external core
power supply.
Table 314. Requirements for Internal/External 1.5-V Core Power Supply
SUPPLY
VCC
3.3 V
VR_EN
VR_PORT
NOTE
Internal 1.5-V LDO-VR is enabled. A 1.0-
μ
F bypass capacitor is required on the VR_PORT
terminal for decoupling. This output is not for external use.
Internal
GND
1.5-V output
External
3.3 V
VCC
1.5-V input
Internal 1.5-V LDO-VR is disabled. An external 1.5-V power supply, of minimum 50-mA
capacity, is required. A 0.1-
μ
F bypass capacitor on the VR_PORT terminal is required.
3.8.3
CardBus (Function 0) Clock Run Protocol
The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI4515 controller.
CLKRUN signaling is provided through the MFUNC6 terminal. Since some chip sets do not implement CLKRUN, this
is not always available to the system designer, and alternate power-saving features are provided. For details on the
CLKRUN protocol see the
PCI Mobile Design Guide
.
The PCI4515 controller does not permit the central resource to stop the PCI clock under any of the following
conditions:
Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set.
The 16-bit PC Card resource manager is busy.
The PCI4515 CardBus master state machine is busy. A cycle may be in progress on CardBus.
The PCI4515 master is busy. There may be posted data from CardBus to PCI in the PCI4515 controller.
Interrupts are pending.
The CardBus CCLK for the socket has not been stopped by the PCI4515 CCLKRUN manager.
Bit 0 (KEEP_PCLK) in the miscellaneous configuration register (PCI offset F0h, see Section 7.21) is set.
The 1394 resource manager is busy.
The PCI4515 1394 master state machine is busy. A cycle may be in progress on 1394.
The PCI4515 master is busy. There may be posted data from the 1394 bus to PCI in the PCI4515 controller.
PC Card interrogation is in progress.
The 1394 bus is not idle.
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| PCI4520ZHK | 制造商:Texas Instruments 功能描述: |
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