- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄378045 > PCI4515GHK (Texas Instruments, Inc.) SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED PDF資料下載
參數(shù)資料
| 型號(hào)： | PCI4515GHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED |
| 中文描述： | 單插槽CardBus控制器，它集成 |
| 文件頁(yè)數(shù)： | 163/216頁(yè) |
| 文件大小： | 1138K |
| 代理商： | PCI4515GHK |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)當(dāng)前第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)
813
8.16 Host Controller Control Register
The host controller control set/clear register pair provides flags for controlling the PCI4515 controller. See Table 811
for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Host controller control
Type
RSU
RSC
RSC
R
R
R
R
R
R
RSC
R
R
RSC
RSC
RSC
RSCU
Default
0
X
0
0
0
0
0
0
1
0
0
0
0
X
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Host controller control
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Host controller control
50h
set register
54h
clear register
Read/Set/Clear/Update, Read/Set/Clear, Read/Clear, Read-only
X08X 0000h
Type:
Default:
Table 811. Host Controller Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
BIBimage Valid
RSU
When bit 31 is set to 1, the PCI4515 physical response unit is enabled to respond to block read
requests to host configuration ROM and to the mechanism for atomically updating configuration
ROM. Software creates a valid image of the bus_info_block in host configuration ROM before
setting this bit.
When this bit is cleared, the PCI4515 controller returns ack_type_error on block read requests
to host configuration ROM. Also, when this bit is cleared and a 1394 bus reset occurs, the
configuration ROM mapping register at OHCI offset 34h (see Section 8.12), configuration ROM
header register at OHCI offset 18h (see Section 8.7), and bus options register at OHCI offset 20h
(see Section 8.9) are not updated.
Software can set this bit only when bit 17 (linkEnable) is 0. Once bit 31 is set to 1, it can be cleared
by a system (hardware) reset, a software reset, or if a fetch error occurs when the PCI4515
controller loads bus_info_block registers from host memory.
30
noByteSwapData
RSC
Bit 30 controls whether physical accesses to locations outside the PCI4515 controller itself, as
well as any other DMA data accesses are byte swapped.
29
AckTardyEnable
RSC
Bit 29 controls the acknowledgement of ack_tardy. When bit 29 is set to 1, ack_tardy may be
returned as an acknowledgment to accesses from the 1394 bus to the PCI4515 controller,
including accesses to the bus_info_block. The PCI4515 controller returns ack_tardy to all other
asynchronous packets addressed to the PCI4515 node. When the PCI4515 controller sends
ack_tardy, bit 27 (ack_tardy) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) is set to 1 to indicate the attempted asynchronous access.
Software ensures that bit 27 (ack_tardy) in the interrupt event register is 0. Software also unmasks
wake-up interrupt events such as bit 19 (phy) and bit 27 (ack_tardy) in the interrupt event register
before placing the PCI4515 controller into the D1 power mode.
Software must not set this bit if the PCI4515 node is the 1394 bus manager.
2824
RSVD
R
Reserved. Bits 2824 return 0s when read.
23
programPhyEnable
R
Bit 23 informs upper-level software that lower-level software has consistently configured the IEEE
1394a-2000 enhancements in the link and PHY layers. When this bit is 1, generic software such
as the OHCI driver is responsible for configuring IEEE 1394a-2000 enhancements in the PHY
layer and bit 22 (aPhyEnhanceEnable). When this bit is 0, the generic software may not modify
the IEEE 1394a-2000 enhancements in the PHY layer and cannot interpret the setting of bit 22
(aPhyEnhanceEnable). This bit is initialized from serial EEPROM. This bit defaults to 1.
This bit is cleared only by the assertion of GRST.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCI4515ZHK | SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED |
| PCI6420 | Integrated 2-Slot PC Card & Dedicated Flash Media Controller |
| PCI6421 | DUAL/SINGLE SOCKET CARDBUS AND ULTRAMEDIA CONTROLLER |
| PCI6611 | DUAL/SINGLE SOCKET CARDBUS AND ULTRAMEDIA CONTROLLER |
| PCI6621 | DUAL/SINGLE SOCKET CARDBUS AND ULTRAMEDIA CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI4515ZHK | 功能描述:IC PC CARD CONTROLLER 257-BGA RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類(lèi)型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| PCI4520 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL-SOCKET PC CARD AND INTEGRATED 1394A-2000 OHCI TWO-PORT PHY/LINK-LAYER CONTROLLER |
| PCI4520GHK | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2 Slot PC Card & int 1394a-2000 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI4520ZHK | 制造商:Texas Instruments 功能描述: |
| PCI-471LF | 制造商:PROTECHSYSTEMS 制造商全稱:PROTECHSYSTEMS 功能描述:PCI ULV Celeron M CPU Card |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。