參數(shù)資料
型號： PCI6515GHK
廠商： Texas Instruments, Inc.
英文描述： SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET
中文描述： 單插槽CardBus控制器，專用智能卡插槽
文件頁數(shù)： 123/148頁
文件大?。?/td> 760K
代理商： PCI6515GHK
67
6.5
Socket Control Register
This register provides control of the voltages applied to the socket V
PP
and V
CC
. The PCI6515 controller ensures that
the socket is powered up only at acceptable voltages when a CardBus card is inserted. See Table 66 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Socket control
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Socket control
Type
R
R
R
R
R
R
RW
R
RW
RW
RW
RW
R
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Socket control
CardBus Socket Address + 10h
Read-only, Read/Write
0000 0000h
Table 66. Socket Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
3111
RSVD
R
These bits return 0s when read.
10
RSVD
R
This bit returns 1 when read.
98
RSVD
R
These bits return 0s when read.
7
STOPCLK
RW
This bit controls how the CardBus clock run state machine decides when to stop the CardBus clock
to the CardBus card:
0 = The CardBus CLKRUN protocol can only attempt to stop/slow the CaredBus clock if the
sockethas been idle for 8 clocks and the PCI CLKRUN protocol is preparing to stop/slow the
PCI bus clock.
1 = The CardBus CLKRUN protocol can only attempt to stop/slow the CaredBus clock if the
socket has been idle for 8 clocks, regardless of the state of the PCI CLKRUN signal.
64
VCCCTRL
RW
VCC control. These bits are used to request card VCC changes.
000 = Request power off (default)
001 = Reserved
010 = Request VCC = 5 V
011 = Request VCC = 3.3 V
This bit returns 0 when read.
100 = Request VCC = X.X V
101 = Request VCC = Y.Y V
110 = Reserved
111 = Reserved
3
RSVD
R
20
VPPCTRL
RW
VPP control. These bits are used to request card VPP changes.
000 = Request power off (default)
001 = Request VPP = 12 V
010 = Request VPP = 5 V
011 = Request VPP = 3.3 V
100 = Request VPP = X.X V
101 = Request VPP = Y.Y V
110 = Reserved
111 = Reserved
One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then this bit is cleared by the assertion of PRST or GRST.
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