參數(shù)資料
型號: PCI6515GHK
廠商: Texas Instruments, Inc.
英文描述: SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET
中文描述: 單插槽CardBus控制器,專用智能卡插槽
文件頁數(shù): 26/148頁
文件大小: 760K
代理商: PCI6515GHK
210
Table 27. PCI Address and Data Terminals
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
M01
M02
M03
M06
M05
N01
N02
N03
P03
R01
R02
P05
R03
T01
T02
W04
W07
R08
U08
V08
W09
V09
U09
R09
V10
U10
R10
W11
V11
U11
P11
R11
I/O
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary
interface. During the address phase of a primary-bus PCI cycle, AD31AD0 contain a 32-bit address or other
destination information. During the data phase, AD31AD0 contain data.
C/BE3
C/BE2
C/BE1
C/BE0
P02
U05
V07
W10
I/O
PCI-bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the
address phase of a primary-bus PCI cycle, C/BE3C/BE0 define the bus command. During the data phase, this
4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry
meaningful data. C/BE0 applies to byte 0 (AD7AD0), C/BE1 applies to byte 1 (AD15AD8), C/BE2 applies to
byte 2 (AD23AD16), and C/BE3 applies to byte 3 (AD31AD24).
PAR
U07
I/O
PCI-bus parity. In all PCI-bus read and write cycles, the controller calculates even parity across the AD31AD0
and C/BE3C/BE0 buses. As an initiator during PCI cycles, the controller outputs this parity indicator with a
one-PCLK delay. As a target during PCI cycles, the controller compares its calculated parity to the parity
indicator of the initiator. A compare error results in the assertion of a parity error (PERR).
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