參數(shù)資料
型號(hào): PCI6515GHK
廠商: Texas Instruments, Inc.
英文描述: SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET
中文描述: 單插槽CardBus控制器,專用智能卡插槽
文件頁(yè)數(shù): 57/148頁(yè)
文件大?。?/td> 760K
代理商: PCI6515GHK
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323
3.8.11 Master List of PME Context Bits and Global Reset-Only Bits
PME context bit means that the bit is cleared only by the assertion of GRST when the PME enable bit, bit 8 of the
power management control/status register (PCI offset A4h, see Section 4.43) is set. If PME is not enabled, then these
bits are cleared when either PRST or GRST is asserted.
The PME context bits (function 0) are:
Bridge control register (PCI offset 3Eh, see Section 4.25): bit 6
System control register (PCI offset 80h, see Section 4.29): bits 108
Power management control/status register (PCI offset A4h, see Section 4.43): bit 15
ExCA power control register (ExCA 802h, see Section 5.3): bits 7, 5 (82365SL mode only), 4, 3, 1, 0
ExCA interrupt and general control (ExCA 803h see Section 5.4): bits 6, 5
ExCA card status-change register (ExCA 804h, see Section 5.5): bits 30
ExCA card status-change interrupt configuration register (ExCA 805h, see Section 5.6): bits 30
ExCA card detect and general control register (ExCA 816h, see Section 5.19): bits 7, 6
Socket event register (CardBus offset 00h, see Section 6.1): bits 30
Socket mask register (CardBus offset 04h, see Section 6.2): bits 30
Socket present state register (CardBus offset 08h, see Section 6.3): bits 137, 51
Socket control register (CardBus offset 10h, see Section 6.5): bits 64, 20
Global reset-only bits, as the name implies, are cleared only by GRST. These bits are never cleared by PRST,
regardless of the setting of the PME enable bit. The GRST signal is gated only by the SUSPEND signal. This means
that assertion of SUSPEND blocks the GRST signal internally, thus preserving all register contents. Figure 312 is
a diagram showing the application of GRST and PRST.
The global reset-only bits (function 0) are:
Status register (PCI offset 06h, see Section 4.5): bits 1511, 8
Secondary status register (PCI offset 16h, see Section 4.14): bits 1511, 8
Subsystem vendor ID register (PCI offset 40h, see Section 4.26): bits 15–0
Subsystem ID register (PCI offset 42h, see Section 4.27): bits 15–0
PC Card 16-bit I/F legacy-mode base-address register (PCI offset 44h, see Section 4.28): bits 310
System control register (PCI offset 80h, see Section 4.29): bits 3124, 2213, 11, 60
General control register (PCI offset 86h, see Section 4.30): bits 1310, 7, 53, 1, 0
General-purpose event status register (PCI offset 88h, see Section 4.31): bits 7, 6, 40
General-purpose event enable register (PCI offset 89h, see Section 4.32): bits 7, 6, 40
General-purpose output register (PCI offset 8Bh, see Section 4.34): bits 40
Multifunction routing register (PCI offset 8Ch, see Section 4.35): bits 310
Retry status register (PCI offset 90h, see Section 4.36): bits 75, 3, 1
Card control register (PCI offset 91h, see Section 4.37): bits 7, 20
Device control register (PCI offset 92h, see Section 4.38): bits 75, 30
Diagnostic register (PCI offset 93h, see Section 4.39): bits 70
Power management capabilities register (PCI offset A2h, see Section 4.42): bit 15
Power management CSR register (PCI offset A4h, see Section 4.43): bits 15, 8
Serial bus data register (PCI offset B0h, see Section 4.46): bits 70
Serial bus index register (PCI offset B1h, see Section 4.47): bits 70
Serial bus slave address register (PCI offset B2h, see Section 4.48): bits 70
Serial bus control/status register (PCI offset B3h, see Section 4.49): bits 7, 30
ExCA identification and revision register (ExCA 800h, see Section 5.1): bits 70
ExCA global control register (ExCA 81Eh, see Section 5.20): bits 20
CardBus socket power management register (CardBus 20h, see Section 6.6): bits 25, 24
The global reset-only (function 5) register bits:
Subsystem vendor ID register (PCI offset 2Ch, see Section 7.9): bits 15–0
Subsystem ID register (PCI offset 2Eh, see Section 7.10): bits 15–0
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