參數(shù)資料
型號： PCK2014ADL
廠商： NXP SEMICONDUCTORS
元件分類： XO, clock
英文描述： CK98 100/133 MHz spread spectrum system clock generator
中文描述： 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 7.50 MM, PLASTIC, SSOP-56
文件頁數(shù)： 10/16頁
文件大?。?/td> 105K
代理商： PCK2014ADL
Philips Semiconductors
Product specification
PCK2014A
CK98 (100/133 MHz) spread spectrum
system clock generator
2001 Apr 02
10
AC CHARACTERISTICS
(Continued)
TEST CONDITIONS
LIMITS
SYMBOL
PARAMETER
T
amb
= 0 to +70
°
C
UNIT
NOTES
Measurement loads
(lumped)
CPU@20 pF,
3V66@30 pF
3V66@30 pF,
PCI@30 pF
CPU@20 pF,
IOAPIC@20 pF
CPU@20 pF
PCI@30 pF
Measure points
MIN
TYP
MAX
T
HPOFFSET
CPUCLK to 3V66 CLK,
CPU leads
3V66 CLK to PCI,
3V66 leads
CPUCLK to APIC,
CPU leads
CPUCLK to PCI,
CPU leads
CPU@1.25 V,
3V66@1.5 V
3V66@1.5 V,
PCI@1.5 V
3CPU@1.25 V,
IOAPIC@1.25 V
CPU@1.25 V
PCI@1.5 V
0.0
0.45
1.5
ns
1
T
HPOFFSET
1.5
2.0
3.5
ns
1
T
HPOFFSET
1.5
2.4
4.0
ns
1
T
HPOFFSET
1.5
2.7
4.0
ns
NOTES:
1. Output drivers must have monotonic rise/fall times through the specified V
OL
/V
OH
levels.
2. Period, jitter, offset and skew measured on rising edge @1.25 V for 2.5 V clocks and @ 1.5 V for 3.3 V clocks.
3. The PCI is the CPUCLK divided by four at CPUCLK = 133 MHz. The 3V66 CLK is internal VCO frequency divided by three at
CPUCLK = 100 MHz.
4. 3V66 CLK is internal VCO frequency divided by two at CPUCLK = 133 MHz. The 3V66 CLK is internal VCO frequency divided by three at
CPUCLK = 100 MHz.
5. T
HKH
is measured at 2.0 V for 2.5 V outputs, 2.4 V for 3.3 V outputs as shown in Figure 4.
6. T
HKL
is measured at 0.4 V for all outputs as shown in Figure 4.
7. The time is specified from when V
DDQ
achieves its nominal operating level (typical condition V
DDQ
= 3.3 V) until the frequency output is
stable and operating within specification.
8. T
HRISE
and T
HFALL
are measured as a transition through the threshold region V
OL
= 0.4 V and V
OH
= 2.4 V for 3 V outputs, V
OL
= 0.4 V, and
V
9. The average period over any 1
μ
s period of time must be greater than the minimum specified period.
10.Calculated at minimum edge-rate (1 V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure
duty-cycle specification is met.
11. Output (see Figure 5 for measure points).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCK2014ADL,112 功能描述:時鐘發(fā)生器及支持產(chǎn)品 CK98(100/133MHZ) SYS CLK GEN RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
PCK2014ADL,118 功能描述:鎖相環(huán) - PLL CK98(100/133MHZ) SYS CLK GEN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
PCK2020 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CK00 100/133MHz spread spectrum differential system clock generator
PCK2020DL 功能描述:時鐘發(fā)生器及支持產(chǎn)品 DN RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
PCK2020DL,512 功能描述:時鐘發(fā)生器及支持產(chǎn)品 DN RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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