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參數(shù)資料
| 型號： | PCK2014ADL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | CK98 100/133 MHz spread spectrum system clock generator |
| 中文描述： | 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 7.50 MM, PLASTIC, SSOP-56 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 105K |
| 代理商： | PCK2014ADL |
Philips Semiconductors
Product specification
PCK2014A
CK98 (100/133 MHz) spread spectrum
system clock generator
2001 Apr 02
5
FUNCTION TABLE
SEL
133/100
0
SEL1
SEL0
CPU
3V66
PCI
48 MHz
REF
IOAPIC
NOTES
0
0
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
1
0
0
1
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
16.67 MHz
2
0
1
0
100 MHz
66 MHz
33 MHz
HI-Z
14.318 MHz
16.67 MHz
3
0
1
1
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
16.67 MHz
4, 7, 8
1
0
0
TCLK/2
TCLK/4
TCLK/8
TCLK/2
TCLK
TCLK/16
5, 6
1
0
1
133 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
16.67 MHz
2
1
1
0
133 MHz
66 MHz
33 MHz
HI-Z
14.318 MHz
16.67 MHz
3
1
1
1
133 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
16.67 MHz
4, 7, 8
NOTES:
1. Required for board level “bed-of-nails” testing.
2. Philips center spread mode.
3. 48 MHz PLL disabled to reduce component jitter. 48 MHz outputs to be held Hi-Z instead of driven to LOW state.
4. “Normal” mode of operation.
5. TCLK is a test clock over driven on the XTALIN input during test mode. TCLK mode is based on 133 MHz CPU select logic.
6. Required for DC output impedance verification.
7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
8. Range of reference frequency allowed is MIN = 14.316 MHz, NOMINAL = 14.31818 MHz, MAX = 14.32 MHz
CLOCK OUTPUT
USBCLK
7
TARGET FREQUENCY (MHz)
ACTUAL FREQUENCY (MHz)
PPM
48.0
48.008
167
CLOCK ENABLE CONFIGURATION
CPUSTOP
PWRDWN
PCISTOP
CPUCLK
APIC
3V66
PCI
REF / 48 MHz
OSC
VCOs
X
0
X
LOW
LOW
LOW
LOW
LOW
OFF
OFF
0
1
0
LOW
ON
LOW
LOW
ON
ON
ON
0
1
1
LOW
ON
LOW
ON
ON
ON
ON
1
1
0
ON
ON
ON
LOW
ON
ON
ON
1
1
1
ON
ON
ON
ON
ON
ON
ON
NOTES:
1. LOW means outputs held static LOW as per latency requirement below
2. ON means active.
3. PWRDWN pulled LOW, impacts all outputs including REF and 48 MHz outputs.
4. All 3V66 clocks as well as CPU clocks should stop cleanly when CPUSTOP is pulled LOW.
5. CPUDIV2, IOAPIC, REF, 48 MHz signals are not controlled by the CPUSTOP functionality and are enabled all in all conditions except when
PWRDWN is LOW.
POWER MANAGEMENT REQUIREMENTS
SIGNAL
SIGNAL STATE
LATENCY
NO. OF RISING EDGES OF FREE RUNNING PCICLK
1
CPUSTOP
0 (DISABLED)
1 (ENABLED)
1
PCISTOP
0 (DISABLED)
1
1 (ENABLED)
1
PWRDWN
1 (NORMAL OPERATION)
3 ms
0 (POWER DOWN)
2 MAX
NOTES:
1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the
first valid clock that comes out of the device.
2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| PCK2014ADL,112 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 CK98(100/133MHZ) SYS CLK GEN RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PCK2014ADL,118 | 功能描述:鎖相環(huán) - PLL CK98(100/133MHZ) SYS CLK GEN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK2020 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CK00 100/133MHz spread spectrum differential system clock generator |
| PCK2020DL | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 DN RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PCK2020DL,512 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 DN RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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