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參數(shù)資料
| 型號(hào)： | PCK2014ADL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | CK98 100/133 MHz spread spectrum system clock generator |
| 中文描述： | 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 7.50 MM, PLASTIC, SSOP-56 |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 105K |
| 代理商： | PCK2014ADL |
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Philips Semiconductors
Product specification
PCK2014A
CK98 (100/133 MHz) spread spectrum
system clock generator
2001 Apr 02
3
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
2, 3
REF [0–1]
3.3 V 14.318 MHz clock output
5
XTAL_IN
14.318 MHz crystal input
6
XTAL_OUT
14.318 MHz crystal output
9, 11, 12, 14, 15, 18
PCI_[F, 1–5]
3.3 V PCI clock outputs, pin 9 is a free running PCI clock
25, 26
3V66 [0–1]
3.3 V fixed 66 MHz clock outputs
28
SEL133/100
Select input pin for enabling 133 MHz or 100 MHz CPU outputs.
H = 133 MHz, L = 100 MHz
3.3 V fixed 48 MHZ clock output
30
48 MHz USB
32, 33
SEL [0–1]
Logic select pins. TTL levels.
34
SPREAD
3.3 V LVTTL input. Enables spread spectrum mode when held LOW.
35
PWRDWN
3.3 V LVTTL input. Device enters powerdown mode when held LOW.
36
CPUSTOP
3.3 V LVTTL input. Stops all CPU clocks and 3V66 clocks when held LOW.
CPUDIV_2 output remains on all the time.
3.3 V LVTTL input. Stops all PCI clocks except PCICLK_F when held LOW.
37
PCISTOP
41, 42, 45, 46, 49, 50
CPUCLK [0–5]
2.5 V CPU output. 133 MHz or 100 MHz depending on state of input pin SEL133/100.
53, 54, 55
APIC [0–2]
2.5 V clock outputs running divide synchronous with the CPU clock frequency.
Fixed 16.67 MHz limit.
4, 10, 16, 17,
22, 23, 27, 31, 39
1, 7, 8, 13, 19, 20, 21, 24,
29, 38, 40, 44, 48, 52
43, 47, 51, 56
NOTE:
1. V
, V
and V
in the above table reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on
the performance of the device. In reality, the platform will be configured with the V
DD25V
pins tied to a 2.5 V supply, all remaining V
DD
pins
tied to a common 3.3 V supply and all V
pins being common.
2. Pins 20 and 21 are analog ground and should be tied to a ground plane. Pins 22 and 23 are analog V
should be properly decoupled
to a 3.3 V supply. These analog power supply pins should not be tied to the PCI power and ground to avoid noise coupling into the
analog power supply pins. The PCK2014 provides separate power supplies for the internal digital circuitry (pin 39, V
CC
) and the internal
PLLs of the device (pins 22 and 23, V
CC
). The purpose of this approach is to try and isolate the high switching noise digital outputs from
relatively sensitive analog blocks. In controlled environments such as a test board this level is very well controlled. However, in a mixed
signal environment, a second level of isolation may be required.
V
DD3V
3.3 V power supply, pins 22 and 23 are analog V
DD
.
V
SS
Ground, pins 20 and 21 are analog V
SS
.
V
DD25V
2.5 V power supply
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCK2014ADL,112 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CK98(100/133MHZ) SYS CLK GEN RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PCK2014ADL,118 | 功能描述:鎖相環(huán) - PLL CK98(100/133MHZ) SYS CLK GEN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK2020 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CK00 100/133MHz spread spectrum differential system clock generator |
| PCK2020DL | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 DN RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PCK2020DL,512 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 DN RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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