參數(shù)資料
型號: PCM1796DBR
元件分類: DAC
英文描述: 24BIT 192 KHZ SAMPLING ADVANCED SEGMENT AUDIO STEREO DIGITAL TO ANALOG CONVERTER
中文描述: 24位192千赫采樣高級分段音頻立體聲數(shù)模轉(zhuǎn)換器
文件頁數(shù): 15/57頁
文件大?。?/td> 512K
代理商: PCM1796DBR
SLES100 DECEMBER 2003
www.ti.com
15
Power-On and External Reset Functions
The PCM1796 includes a power-on reset function. Figure 24 shows the operation of this function. With V
DD
> 2 V,
the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time
V
DD
> 2 V. After the initialization period, the PCM1796 is set to its default reset state, as described in the
MODE
CONTROL REGISTERS
section of this data sheet.
The PCM1796 also includes an external reset capability using the RST input (pin 14). This allows an external
controller or master reset circuit to force the PCM1796 to initialize to its default reset state.
Figure 25 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The
RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock
periods. The external reset is especially useful in applications where there is a delay between the PCM1796 power
up and system clock activation.
Reset
Reset Removal
1024 System Clocks
VDD
2.4 V (Max)
2.0 V (Typ)
1.6 V (Min)
Internal Reset
System Clock
Figure 24. Power-On Reset Timing
Reset
Reset Removal
1024 System Clocks
Internal Reset
System Clock
RST (Pin 14)
t(RST)
1.4 V
PARAMETERS
MIN
20
MAX
UNITS
ns
t(RST)
Reset pulse duration, LOW
Figure 25. External Reset Timing
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PCM1798 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-BIT, 192-KHZ SAMPLING ADVANCED SEGMENT, AUDIO STEREO DIGITAL TO ANALOG CONVERTER
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