參數(shù)資料
型號(hào): PCM1796DBR
元件分類: DAC
英文描述: 24BIT 192 KHZ SAMPLING ADVANCED SEGMENT AUDIO STEREO DIGITAL TO ANALOG CONVERTER
中文描述: 24位192千赫采樣高級(jí)分段音頻立體聲數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù): 16/57頁(yè)
文件大?。?/td> 512K
代理商: PCM1796DBR
SLES100 DECEMBER 2003
www.ti.com
16
AUDIO DATA INTERFACE
Audio Serial Interface
The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the
serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio
interface. Serial data is clocked into the PCM1796 on the rising edge of BCK. LRCK is the serial audio left/right word
clock.
The PCM1796 requires the synchronization of LRCK and system clock, but does not need a specific phase relation
between LRCK and system clock.
If the relationship between LRCK and system clock changes more than
±
6 BCK, internal operation is initialized within
1/f
S
and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and system clock
is completed.
PCM Audio Data Formats and Timing
The PCM1796 supports industry-standard audio data formats, including standard right-justified, I
2
S, and
left-justified. The data formats are shown in Figure 27. Data formats are selected using the format bits, FMT[2:0],
in control register 18. The default data format is 24-bit I
2
S. All formats require binary 2s complement, MSB-first audio
data. Figure 26 shows a detailed timing diagram for the serial audio interface.
DATA
t(BCH)
1.4 V
BCK
LRCK
t(BCL)
t(LB)
t(BCY)
t(DS)
t(DH)
1.4 V
1.4 V
t(BL)
PARAMETERS
MIN
70
MAX
UNITS
ns
t(BCY)
t(BCL)
t(BCH)
t(BL)
t(LB)
t(DS)
t(DH)
BCK pulse cycle time
BCK pulse duration, LOW
30
ns
BCK pulse duration, HIGH
30
ns
BCK rising edge to LRCK edge
10
ns
LRCK edge to BCK rising edge
10
ns
DATA setup time
10
ns
DATA hold time
10
50%
±
2 bit clocks
ns
LRCK clock data
Figure 26. Timing of Audio Interface
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相關(guān)代理商/技術(shù)參數(shù)
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