參數(shù)資料
型號(hào)： PCM3168ATPAPRQ1G4
廠商： Texas Instruments
文件頁(yè)數(shù)： 22/68頁(yè)
文件大?。?/td> 0K
描述： IC 24-BIT AUDIO CODEC 64-HTQFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 音頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 6 / 8
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 107 / 112（差分），104 / 112（單端）
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 107 / 112（差分），104 / 112（單端）
電壓 - 電源，模擬： 4.5 V ~ 5.5 V
電壓 - 電源，數(shù)字： 3 V ~ 3.6 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 64-HTQFP（10x10）
包裝： 帶卷 (TR)
SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM
Stateof
Synchronization
Synchronous
Normal
ZERO
Normal
Synchronous
Asynchronous
DAC
VOUTX±
ADC
DOUTX
VCOMDA
(0.5VCCDA1)
Within1/f
S
t
ADCDLY3
t
DACDLY3
UndefinedData
HIGH-PASS FILTER (HPF)
www.ti.com ......................................................................................................................................................................................... SBAS452 – SEPTEMBER 2008
The PCM3168A and PCM3168A-Q1 operate under the system clock (SCKI) and the audio sampling rate
(LRCKAD/DA). Therefore, SCKI and LRCKAD/DA must have a specific relationship in slave mode. The
PCM3168A and PCM3168A-Q1 do not need a specific phase relationship between the audio interface clocks
(LRCKAD/DA, BCKAD/DA) and the system clock (SCKI), but does require a specific frequency relationship
(ratiometric) between LRCKAD/DA, BCKAD/DA, and SCKI.
If the relationship between SCKI and LRCKDA changes more than ±2 BCKDA clocks because of jitter, sampling
frequency change, etc., the DAC internal operation halts within 1/fS, and the analog output is forced into
VCOMDA (0.5 VCCDA1) until re-synchronization between SCKI, LRCKDA, and BCKDA is completed and then
tDACDLY3 passes. If the relationship between SCKI and LRCKAD changes more than ±2 BCKADs because of
jitter, sampling frequency change, etc., the ADC internal operation halts within 1/fS, and the digital output is
forced into a '0' code until re-synchronization between SCKI, LRCKAD, and BCKAD is completed and then
tADCDLY3 passes. In the event the change is less than ±2 BCKAD/DAs, re-synchronization does not occur, and
this analog/digital output control and discontinuity do not occur.
Figure 46 shows the DAC analog output and ADC digital output for loss of synchronization. During undefined
data periods, some noise may be generated in the audio signal. Also, the transition of normal to undefined data
and undefined (or zero) data to normal data creates a discontinuity of data on the analog and digital outputs,
which then may generate some noise in the audio signal.
Both ADC outputs (DOUTx) and DAC outputs (VOUTx) hold the previous state if the system clock halts, but the
asynchronous and re-synchronization processes would occur after the system clock resumes. Figure 46 shows
DAC outputs and ADC outputs for loss of synchronization.
Figure 46. DAC Outputs and ADC Outputs for Loss of Synchronization
Timing Requirements for Figure 46
SYMBOL
DESCRIPTION
SINGLE
DUAL
QUAD
UNIT
Period of
tDACDLY3
DAC delay synchronization detect to normal data
38
29
LRCKDA
Period of
tADCDLY3
ADC delay synchronization detect to normal data
60
N/A
LRCKAD
The PCM3168A and PCM3168A-Q1 include a high-pass filter (HPF) for all ADC channels in order to remove the
dc component of the digitized input signal. The filter is located at the output of the digital decimation filter. The –3
dB corner frequency for the HPF scales with the output sampling rate, where f–3 dB = 0.020 × fS/1000. When fS =
48 kHz, f–3 dB is 0.96 Hz. The HPF function can be disabled (bypassed) by the BYP bits in two channels.
Copyright 2008, Texas Instruments Incorporated
29
Product Folder Link(s): PCM3168A PCM3168A-Q1
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