SBAS452 – SEPTEMBER 2008
參數(shù)資料
型號(hào)： PCM3168ATPAPRQ1G4
廠商： Texas Instruments
文件頁(yè)數(shù)： 24/68頁(yè)
文件大?。?/td> 0K
描述： IC 24-BIT AUDIO CODEC 64-HTQFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 音頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 6 / 8
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 107 / 112（差分），104 / 112（單端）
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 107 / 112（差分），104 / 112（單端）
電壓 - 電源，模擬： 4.5 V ~ 5.5 V
電壓 - 電源，數(shù)字： 3 V ~ 3.6 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 64-HTQFP（10x10）
包裝： 帶卷 (TR)
OVERFLOW FLAG
ZERO FLAG
MODE CONTROL
HARDWARE CONTROL MODE CONFIGURATION
SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com
The PCM3168A and PCM3168A-Q1 include an overflow flag output for all ADC channels. As soon as any of the
six-channel ADC digital outputs exceed the full-scale range, an overflow flag is forced high on the OVF pin. The
overflow flag is held high for 1024 LRCKAD clock cycles. In parallel, overflow flag information is stored in the
OVF bits of the mode control register, and the OVF bit is held until the mode control register is read. The
overflow flag polarity can be changed by the OVFP bit. The OVF pin also indicates internal reset completion by
transmitting a 4096 SCKI width pulse.
The PCM3168A and PCM3168A-Q1 include a zero flag output for all DAC channels. When all of the
eight-channel DACs digital inputs have continued as zero data for 1024 LRCKDA clock cycles, the zero flag is
forced high on ZERO. In parallel, zero flag information is stored in the ZERO bits according to channel. The zero
flag polarity can be changed by the ZREV bit. Also, the zero flag function can be selected by the AZRO bits.
AND or OR logic for stereo, six channels, and eight channels can be selected.
The PCM3168A and PCM3168A-Q1 include four-way mode control selectable by MODE pin, as shown in
Table 10. The pull-up and pull-down resistors must be 220 k
±5%. This mode control selection is sampled only
when the internal reset is released by a power-on reset or by a low-to-high transition of the external reset (RST
pin); a system clock is also required.
Table 10. Mode Control Selection
MODE
MODE CONTROL INTERFACE
Tied to DGND
Two-wire (I2C) serial control, selectable analog input configuration
Tied to DGND via pull-down resistor
H/W (hardware control), differential analog input
Tied to VDD via pull-up resistor
H/W (hardware control), single-ended analog input
Tied to VDD
Four-wire (SPI) serial control, selectable analog input configuration
From the mode control selection described in Table 10, the functions of four pins are changed, as shown in
Table 11. Pin Functions
PIN ASSIGNMENTS
PIN
SPI
I2C
H/W
MS/ADR0/MD0
MS
ADR0
MD0
MDO/ADR1/MD1
MDO
ADR1
MD1
MDI/SDA/DEMP
MDI
SDA
DEMP
MC/SCL/FMT
MC
SCL
FMT
Both serial controls are available while RST = high and after internal reset completion, which is indicated as a
negative transition (high
≥ low) of a 4096 × SCKI width pulse on the OVF pin.
The data format is selected by the MC/SCL/FMT pin between I2S format and I2S mode in TDM format, as shown
Table 12. Data Format Selection
FMT
MODE CONTROL INTERFACE
Low
I2S audio data format
High
I2S mode, TDM audio data format (supported only for SCKI = 128 fS, 256 fS, or 512 fS)
30
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): PCM3168A PCM3168A-Q1
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