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參數(shù)資料
| 型號： | PCM4222PFBRG4 |
| 英文描述： | High-Performance, Two-Channel, 24-Bit, 216kHz Sampling Multi-Bit Delta-Sigma Analog-to-Digital Converter |
| 中文描述： | 高性能，雙通道，24位，216kHz的采樣多位Δ-Σ模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 21/40頁 |
| 文件大?。?/td> | 609K |
| 代理商： | PCM4222PFBRG4 |
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PCM4222
SBAS399A–OCTOBER 2006–REVISED MARCH 2007
Table 3. PCM Audio Data Format Selection
FMT1 (pin 43)
LO
LO
HI
HI
FMT0 (pin 44)
LO
HI
LO
HI
AUDIO DATA FORMAT
Left-Justified
I
2
S
TDM
TDM with data delayed one BCK cycle from LRCK rising edge
The LRCK clock rate should always be operated at the desired output sampling rate, or f
S
. In Slave mode, the
LRCK clock is an input, with the rate set by an external audio bus master (that is, a clock generator, digital
signal processor, etc.). In Master mode, the LRCK clock is an output, derived from the master clock input using
on-chip clock dividers (as is the BCK clock). The clock divider is configured using the FS0 and FS1 pins, which
are discussed in the
PCM Output and Sampling Modes
section of this datasheet.
For the I
2
S and Left-Justified data formats, the BCK clock output rate is fixed in Master mode, with the Normal
mode being 128f
S
and the Double and Quad Speed modes being 64f
S
. In Slave Mode, a BCK clock input rate of
64f
S
or 128f
S
is recommended for Normal mode, while 64f
S
is recommended for Double and Quad Rate modes.
For the TDM data formats, the BCK rate depends upon the sampling mode for either Slave or Master operation.
For Normal sampling, the BCK must be 256f
S
. Double Speed mode requires 128f
S
, while Quad Speed mode
requires 64f
S
. This requirement limits the maximum number of channels carried by the TDM formats to eight for
Normal mode, four for Double Rate mode, and two for Quad Rate mode.
When using the TDM formats, the sub-frame assignment for the device must be selected using the SUB0 and
SUB1 inputs (pins 26 and 25, respectively).
Table 4
summarizes the sub-frame selection options. A sub-frame
contains two 32-bit time slots, with each time slot carrying 24-bits of audio data corresponding to either the left
or right channel of the PCM4222. Refer to
Figure 43
through
Figure 45
for TDM interfacing connections and
sub-frame formatting details. For the TDM format with one BCK delay, the serial data output is delayed by one
BCK period after the rising edge of the LRCK clock.
Table 4. TDM Sub-frame Assignment
SUB1 (pin 25)
LO
LO
HI
HI
SUB0 (pin 26)
LO
HI
LO
HI
SUB-FRAME ASSIGNMENT
Sub-frame 0
Sub-frame 1
Sub-frame 2
Sub-frame 3
When using TDM formats with Double Speed sampling, it is recommended that the SUB1 pin be forced low.
When using TDM formats with Quad Speed sampling, it is recommended that both the SUB0 and SUB1 pins be
forced low.
For all serial port modes and data formats, when driving capacitive loads greater than 30pF with the data and
clock outputs, it is recommended that external buffers be utilized to ensure data and clock integrity at the
receiving device(s).
For specifications regarding audio serial port operation, the reader is referred to the
Electrical Characteristics
:
Audio Interface Timing table, as well as
Figure 1
and
Figure 2
in this datasheet.
21
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