參數(shù)資料
型號(hào): PENTIUM
元件分類: 開關(guān)穩(wěn)壓
英文描述: Dual High Efficiency, Low Noise, Synchronous Step-Down Switching Regulators
中文描述: 雙通道高效率,低噪聲,同步降壓型開關(guān)穩(wěn)壓器
文件頁數(shù): 12/70頁
文件大?。?/td> 1322K
代理商: PENTIUM
PENTIUM PROCESSOR 75/90/100/120/133/150/166/200
E
12
Table 1. Pin Cross Reference by Pin Name
(Continued)
Control
VSS
B06
B22
M02
U35
AB36
AM08
AM24
B08
B24
M36
V02
AD02
AM10
AM26
B10
B26
P02
V36
AD36
AM12
AM28
B12
B28
P36
X02
AF02
AM14
AM30
B14
H02
R02
X36
AF36
AM16
AN37
B16
H36
R36
Z02
AH02
AM18
B18
K02
T02
Z36
AJ37
AM20
B20
K36
T36
AB02
AL37
AM22
NC/INC
1
A03
C01
S35
W35
AL01
AN01
AN05
A37
R34
W33
AL19
AN03
AN35
B02
S33
NOTE:
1.
Please refer to socket 5 and socket 7 specifications if using socket 5 or socket 7.
2.2.
Design Notes
For reliable operation, always connect unused inputs
to an appropriate signal level. Unused active low
inputs should be connected to V
CC
. Unused active
HIGH inputs should be connected to GND.
No Connect (NC) pins must remain unconnected.
Connection of NC pins may result in component
failure or incompatibility with processor steppings.
2.3.
Quick Pin Reference
This section gives a brief functional description of
each of the pins. For a detailed description, see the
“Hardware Interface” chapter in the Pentium
Processor Family Developer’s Manual Volume 1.
Note
All input pins must meet their AC/DC
specifications to guarantee proper functional
behavior.
The # symbol at the end of a signal name indicates
that the active, or asserted state occurs when the
signal is at a low voltage. When a # symbol is not
present after the signal name, the signal is active, or
asserted at the high voltage level.
The following pins exist on the Pentium processor
60/66 but have been removed from the Pentium
processor 75/90/100/120/133/150/166/200:
IBT, IU, IV, BT0-3
The following pins become I/O pins when two
Pentium processors 75/90/100/120/133/150/166/200
are operating in a dual processing environment:
ADS#, CACHE#, HIT#, HITM#, HLDA#, LOCK#,
M/IO#, D/C#, W/R#, SCYC
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