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參數(shù)資料
| 型號： | PENTIUM |
| 元件分類： | 開關(guān)穩(wěn)壓 |
| 英文描述： | Dual High Efficiency, Low Noise, Synchronous Step-Down Switching Regulators |
| 中文描述： | 雙通道高效率，低噪聲，同步降壓型開關(guān)穩(wěn)壓器 |
| 文件頁數(shù)： | 13/70頁 |
| 文件大?。?/td> | 1322K |
| 代理商： | PENTIUM |
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E
PENTIUM PROCESSOR 75/90/100/120/133/150/166/200
13
Table 2. Quick Pin Reference
Symbol
Type*
Name and Function
A20M#
I
When the
address bit 20 mask
pin is asserted, the Pentium processor
75/90/100/120/133/150/166/200 emulates the address wraparound at 1 Mbyte
which occurs on the 8086 by masking physical address bit 20 (A20) before
performing a lookup to the internal caches or driving a memory cycle on the bus.
The effect of A20M# is undefined in protected mode. A20M# must be asserted
only when the processor is in real mode.
A20M# is internally masked by the Pentium processor 75/90/100/120/133/150/
166/200 when configured as a Dual processor.
A31-A3
I/O
As outputs, the
address
lines of the processor along with the byte enables define
the physical area of memory or I/O accessed. The external system drives the
inquire address to the processor on A31-A5.
ADS#
O
The
address status
indicates that a new valid bus cycle is currently being driven
by the Pentium processor 75/90/100/120/133/150/166/200.
ADSC#
O
ADSC# is functionally identical to ADS#.
AHOLD
I
In response to the assertion of
address hold
, the Pentium processor
75/90/100/120/133/150/166/200 will stop driving the address lines (A31-A3), and
AP in the next clock. The rest of the bus will remain active so data can be returned
or driven for previously issued bus cycles.
AP
I/O
Address parity
is driven by the Pentium processor
75/90/100/120/133/150/166/200 with even parity information on all Pentium
processor 75/90/100/120/133/150/166/200 generated cycles in the same clock
that the address is driven. Even parity must be driven back to the Pentium
processor 75/90/100/120/133/150/166/200 during inquire cycles on this pin in the
same clock as EADS# to ensure that correct parity check status is indicated by
the Pentium processor 75/90/100/120/133/150/166/200.
APCHK#
O
The
address parity check
status pin is asserted two clocks after EADS# is
sampled active if the Pentium processor 75/90/100/120/133/150/166/200 has
detected a parity error on the address bus during inquire cycles. APCHK# will
remain active for one clock each time a parity error is detected (including during
dual processing private snooping).
[APICEN]
PICD1
I
Advanced Programmable Interrupt Controller Enable
enables or disables the
on-chip APIC interrupt controller. If sampled high at the falling edge of RESET, the
APIC is enabled. APICEN shares a pin with the PICD1 signal.
BE7#-BE5#
BE4#-BE0#
O
I/O
The
byte enable
pins are used to determine which bytes must be written to
external memory, or which bytes were requested by the CPU for the current cycle.
The byte enables are driven in the same clock as the address lines (A31-3).
Additionally, the lower 4-byte enables (BE3#-BE0#) are used on the Pentium
processor 75/90/100/120/133/150/166/200 as APIC ID inputs and are sampled at
RESET.
In dual processing mode, BE4# is used as an input during Flush cycles.
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