參數(shù)資料
型號(hào)： PENTIUM
元件分類： 開(kāi)關(guān)穩(wěn)壓
英文描述： Dual High Efficiency, Low Noise, Synchronous Step-Down Switching Regulators
中文描述： 雙通道高效率，低噪聲，同步降壓型開(kāi)關(guān)穩(wěn)壓器
文件頁(yè)數(shù)： 16/70頁(yè)
文件大?。?/td> 1322K
代理商： PENTIUM
PENTIUM PROCESSOR 75/90/100/120/133/150/166/200
E
16
Table 2. Quick Pin Reference
(Continued)
Symbol
Type*
Name and Function
[DPEN#]
PICD0
I/O
Dual processing enable
is an output of the Dual processor and an input of the
Primary processor. The Dual processor drives DPEN# low to the Primary
processor at RESET to indicate that the Primary processor should enable dual
processor mode. DPEN# may be sampled by the system at the falling edge of
RESET to determine if the dual-processor socket is occupied. DPEN# shares a
pin with PICD0.
EADS#
I
This signal indicates that a valid
external address
has been driven onto the
Pentium processor 75/90/100/120/133/150/166/200 address pins to be used for an
inquire cycle.
EWBE#
I
The
external write buffer empty
input, when inactive (high), indicates that a write
cycle is pending in the external system. When the Pentium processor 75/90/100/
120/133/150/166/200 generates a write, and EWBE# is sampled inactive, the
Pentium processor 75/90/100/120/133/150/166/200 will hold off all subsequent
writes to all E- or M-state lines in the data cache until all write cycles have
completed, as indicated by EWBE# being active.
FERR#
O
The
floating point error
pin is driven active when an unmasked floating point
error occurs. FERR# is similar to the ERROR# pin on the Intel387 math
coprocessor. FERR# is included for compatibility with systems using DOS type
floating point error reporting. FERR# is never driven active by the Dual processor.
FLUSH#
I
When asserted, the
cache flush
input forces the Pentium processor 75/90/100/
120/133/150/166/200 to write back all modified lines in the data cache and
invalidate its internal caches. A Flush Acknowledge special cycle will be
generated by the Pentium processor 75/90/100/120/133/150/166/200 indicating
completion of the write back and invalidation.
If FLUSH# is sampled low when RESET transitions from high to low, tristate test
mode is entered.
If two Pentium processor 75/90/100/120/133/150/166/200 are operating in dual
processing mode and FLUSH# is asserted, the Dual processor will perform a flush
first (without a flush acknowledge cycle), then the Primary processor will perform
a flush followed by a flush acknowledge cycle.
NOTE:
If the FLUSH# signal is asserted in dual processing mode, it must be deasserted
at least one clock prior to BRDY# of the FLUSH Acknowledge cycle to avoid DP
arbitration problems.
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