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參數(shù)資料
| 型號： | PENTIUM |
| 元件分類： | 開關(guān)穩(wěn)壓 |
| 英文描述： | Dual High Efficiency, Low Noise, Synchronous Step-Down Switching Regulators |
| 中文描述： | 雙通道高效率，低噪聲，同步降壓型開關(guān)穩(wěn)壓器 |
| 文件頁數(shù)： | 19/70頁 |
| 文件大?。?/td> | 1322K |
| 代理商： | PENTIUM |
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E
PENTIUM PROCESSOR 75/90/100/120/133/150/166/200
19
Table 2. Quick Pin Reference
(Continued)
Symbol
Type*
Name and Function
LOCK#
O
The
bus lock
pin indicates that the current bus cycle is locked. The Pentium
processor 75/90/100/120/133/150/166/200 will not allow a bus hold when LOCK#
is asserted (but AHOLD and BOFF# are allowed). LOCK# goes active in the first
clock of the first locked bus cycle and goes inactive after the BRDY# is returned
for the last locked bus cycle. LOCK# is guaranteed to be de-asserted for at least
one clock between back-to-back locked cycles.
M/IO#
O
The
memory/input-output
is one of the primary bus cycle definition pins. It is
driven valid in the same clock as the ADS# signal is asserted. M/IO# distinguishes
between memory and I/O cycles.
NA#
I
An active
next address
input indicates that the external memory system is ready
to accept a new bus cycle although all data transfers for the current cycle have
not yet completed. The Pentium processor 75/90/100/120/133/150/166/200 will
issue ADS# for a pending cycle two clocks after NA# is asserted. The Pentium
processor 75/90/100/120/133/150/166/200 supports up to 2 outstanding bus
cycles.
NMI/LINT1
I
The
non-maskable interrupt
request signal indicates that an external non-maskable
interrupt has been generated.
If the local APIC is enabled, this pin becomes LINT1.
PBGNT#
I/O
Private bus grant
is the grant line that is used when two Pentium processor
75/90/100/120/133/150/166/200 are configured in dual processing mode, in order
to perform private bus arbitration. PBGNT# should be left unconnected if only one
Pentium processor 75/90/100/120/133/150/166/200 exists in a system.
PBREQ#
I/O
Private bus request
is the request line that is used when two Pentium processor
75/90/100/120/133/150/166/200 are configured in dual processing mode, in order
to perform private bus arbitration. PBREQ# should be left unconnected if only one
Pentium processor 75/90/100/120/133/150/166/200 exists in a system.
PCD
O
The
page cache disable
pin reflects the state of the PCD bit in CR3, the Page
Directory Entry, or the Page Table Entry. The purpose of PCD is to provide an
external cacheability indication on a page by page basis.
PCHK#
O
The
parity check
output indicates the result of a parity check on a data read. It is
driven with parity status two clocks after BRDY# is returned. PCHK# remains low
one clock for each clock in which a parity error was detected. Parity is checked
only for the bytes on which valid data is returned.
When two Pentium processor 75/90/100/120/133/150/166/200 are operating in
dual processing mode, PCHK# may be driven two or three clocks after BRDY# is
returned.
PEN#
I
The
parity enable
input (along with CR4.MCE) determines whether a machine
check exception will be taken as a result of a data parity error on a read cycle. If
this pin is sampled active in the clock a data parity error is detected, the Pentium
processor 75/90/100/120/133/150/166/200 will latch the address and control
signals of the cycle with the parity error in the machine check registers. If, in
addition, the machine check enable bit in CR4 is set to “1”, the Pentium processor
75/90/100/120/133/150/166/200 will vector to the machine check exception before
the beginning of the next instruction.
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