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| 型號： | PF38F3050L0YUQ3A |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封裝： | 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88 |
| 文件頁數(shù)： | 29/70頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | PF38F3050L0YUQ3A |
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Intel StrataFlash Wireless Memory (L18 SCSP)
August 2006
Datasheet
Order Number: 314476-001
35
768-Mbit LQ Family with Synchronous PSRAM
8.0
Synchronous PSRAM AC Characteristics
The figures and tables below shows the PSRAM AC characteristics. All timing
parameters are measured with the default output drive strength (half drive strength).
8.1
PSRAM Asynchronous Read
Notes:
1.
Timing parameters are at the default output drive strength (half drive strength).
2.
tCSL max limit applies during asynchronous reads when page mode is enabled.
3.
Applies to ADV# controlled Asynchronous Read operations.
4.
Applies when control signals (ADV#, CS#, UB#/LB#) are active.
5.
When operating the PSRAM as an ADMux I/O interface, Page-Mode operation is not available.
Table 15. PSRAM AC Characteristics—Asynchronous Read
Symbol
Parameter
85 ns PSRAM
70 ns PSRAM
Units Notes
Min
Max
Min
Max
tRC
Read Cycle Time
85
—
70
—
ns
1
tAA
Address Access Time
—
85
—
70
ns
1
t
AADV
ADV# Access Time
—
85
—
70
ns
1
tPC
Page Address Cycle Time
25
—
20
—
ns
1,5
tPAA
Page Address Access Time
—
25
—
20
ns
1,5
t
AVH
Address Hold from ADV# High
—
5
—
ns
1,3
tAVS
Address Setup to ADV# High
—
10
—
ns
1,3
tCVS
CE# Low to ADV# High
—
10
—
ns
1,3
t
OH
Output Hold from Address Change
6
—
5
—
ns
1
tCO
CE# Access Time
—
85
—
70
ns
1
tBA
UB#, LB# Access Time
—
85
—
70
ns
1
t
OE
OE# to Valid Output Data
—
20
—
20
ns
1
tCSL
CE# Pulse Width Low Time
—
10
—
4
s
1,2
tLZ
CE# Low to Output Low-Z
10
—
6
—
ns
1
t
HZ
CE# High to Output High-Z
0
8
0
8
ns
1
tBLZ
UB#, LB# Low to Output Low-Z
10
—
6
—
ns
1
tBHZ
UB#, LB# High to Output High-Z
—
8
0
8
ns
1
t
OLZ
OE# Low to Output Low-Z
5
—
3
—
ns
1
tOHZ
OE# High to Output HIgh-Z
0
—
0
8
ns
1
tVP
ADV# Pulse Width Low
—
10
—
ns
1,3
t
VPH
ADV# Pulse Width High
10
—
10
—
ns
1,3
tCPH
UB#, LB# and CE# Pulse Width High
15
—
10
—
ns
1
tCRES
CRE Setup to CE# Low
—
0
—
ns
1
t
ASKEW
Address Skew (Non-Page Access)
—
10
ns
1,4
tASKEWP Page Mode Access Address Skew [A3:A0]
—
2
ns
1,5
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