參數(shù)資料
型號: PF38F3050L0YUQ3A
廠商: INTEL CORP
元件分類: 存儲器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA88
封裝: 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88
文件頁數(shù): 61/70頁
文件大?。?/td> 1193K
代理商: PF38F3050L0YUQ3A
768-Mbit LQ Family with Synchronous PSRAM
Intel StrataFlash Wireless Memory (L18 SCSP)
Datasheet
August 2006
64
Order Number: 314476-001
768-Mbit LQ Family with Synchronous PSRAM
12.4
PSRAM Self-Refresh Operation
Unlike DRAMs, The PSRAM relieves the host system from issuing refresh commands.
Self-refresh operations are autonomously scheduled and performed by the PSRAM
device. In synchronous mode of operations (variable latency Read), the additional
WAIT cycles are used to indicate when the data output is delayed in case a burst
initiated access collides with an ongoing refresh cycle.
12.4.1
PSRAM Self-Refresh Operations at Low Frequency
At low frequencies (< 100 KHz ), the PSRAM can support only asynchronous read (non-
page and non-burst modes) operations. All other operations (asynchronous writes,
page-mode reads, and synchronous burst-mode accesses) are subject to refresh
restrictions.
12.5
PSRAM Burst Suspend, Interrupt, or Termination
12.5.1
PSRAM Burst Suspend
While in synchronous burst operation, the bus interface may need to be assigned to
other memory transaction sharing the same bus. Burst suspend is used to fulfill this
purpose. Keeping CE# low (WAIT stays active although the DQ are tri-stated), burst
suspend is initiated by halting CLK. CLK can stay at either high or low state. Burst
suspend may also by initiated while WAIT is asserted during the initial latency period or
at the end of a row.
As specified, duration of keeping CE# low can not exceed tCSL maximum so that
internal refresh operation is able to run properly. In the event that tCSL maximum may
be exceeded, termination of burst by bringing CE# high is strongly recommended
instead of using burst suspend mode.
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