參數(shù)資料
型號: PF38F3050L0YUQ3A
廠商: INTEL CORP
元件分類: 存儲器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA88
封裝: 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88
文件頁數(shù): 33/70頁
文件大小: 1193K
代理商: PF38F3050L0YUQ3A
Intel StrataFlash Wireless Memory (L18 SCSP)
August 2006
Datasheet
Order Number: 314476-001
39
768-Mbit LQ Family with Synchronous PSRAM
Notes:
1.
WE# Low time must be limited to tCSL Max.
2.
For ADV# controlled Async Write operation.
3.
Applies when control signals (ADV#, CE#, UB#, LB#) are Active.
4.
For ADV# controlled write tAVS and tAVH apply to CRE signal instead of tCRES and tCREH.
tWPH
WE# Pulse Width High
15
10
ns
tCPH
UB#, LB# and CE# Pulse Width High
15
10
ns
t
WHZ
Write Enable Low to Output High-Z
0
10
8
ns
tOW
End of Write to Output Low-Z
5
5
ns
tDW
Write Data Setup Time
20
23
ns
t
DH
Write Data Hold Time
0
0
ns
tCRES
CRE SetupTime to CE# and WE# Low
5
0
ns
4
tCREH
CRE Hold Time From WE# High
0
0
ns
4
t
ASKEW
Address Skew (Non-Page Access)
10
ns
3
Table 16. PSRAM AC Characteristics—Asynchronous Write (Sheet 2 of 2)
Symbol
Parameter
85 ns PSRAM
70 ns PSRAM
Units Notes
MinMax
Figure 17. PSRAM Asynchronous WE# controlled Write
tOW
tD H
tD W
tWH Z
tLZ
tBLZ
tBW
tWPH
tWP
tAS
tWP
tC W
tVS
tWR
tWC
tAW
tWC
A[M AX:0]
AD V#
CE #
WE#
UB #/LB#
DQ [15:0]
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