參數(shù)資料
型號(hào)： PF38F3050L0YUQ3A
廠商： INTEL CORP
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA88
封裝： 8 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, SCSP-88
文件頁數(shù)： 43/70頁
文件大?。?/td> 1193K
代理商： PF38F3050L0YUQ3A
768-Mbit LQ Family with Synchronous PSRAM
Intel StrataFlash Wireless Memory (L18 SCSP)
Datasheet
August 2006
48
Order Number: 314476-001
768-Mbit LQ Family with Synchronous PSRAM
11.0
PSRAM Bus Interface
The PSRAM bus interface supports asynchronous and synchronous read and write
transfers. By default the PSRAM device is reset to the asynchronous SRAM-type mode
after power-up. To put the device in a different operation mode the Bus Configuration
Register must be programmed first accordingly.
11.1
PSRAM Reads
The PSRAM bus interface supports asynchronous single-word, asynchronous page-
mode, and synchronous burst-mode reads. PSRAM Refresh Control Register bit 7
(RCR7) defines whether page-mode reads are enabled. Page-mode reads are enabled
when RCR7 is set to a one, and disabled when RCR7 is set to zero.
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, Page-Mode operation cannot be used. RCR7
must be set to Zero.
11.1.1
PSRAM Asynchronous Read
To initiate an asynchronous read operation:
CE#, OE#, and UB#/LB# must be asserted.
WE# and CRE must be deasserted.
ADV# can be toggled to latch the address or held low for the entire read operation.
CLK must be held in a static state.
Valid data is available on the data bus after the specified access time has elapsed.
WAIT output is driven, but should be ignored for asynchronous-mode read operations.
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
11.1.2
PSRAM Asynchronous Page-Mode Read
Page mode allows toggling of the four lower address bits (A3 to A0) to perform
subsequent random read accesses (max. 16-words by A3-A0) at much faster speed
than the 1st read access. Only page mode Read operations are supported by the
PSRAM. Once page mode is enabled by appropriately setting the BCR, tCSL restrictions
will apply to asynchronous Read accesses. Therefore CE# will have to be pulled high at
least every tCSL period during asynchronous Read operations. ADV# has to be held low
for the entire page operation.
Warning:
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, Page-Mode operation cannot be used. RCR7
must be set to Zero.
11.1.3
PSRAM Synchronous Burst-Mode Reads
In the Full Synchronous mode and NOR-Flash mode, PSRAM read operations are
synchronous. A BURST INIT READ command is used to initiate a synchronous read
operation and latch the burst start address. To initiate a synchronous read operation:
CE#, ADV#, and both UB# and LB# must be asserted;
WE# and CRE must be deasserted; and
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