參數(shù)資料
型號(hào)： PIC16C712-04/SO
廠商： Microchip Technology
文件頁(yè)數(shù)： 14/106頁(yè)
文件大小： 0K
描述： IC MCU OTP 1KX14 A/D PWM 18SOIC
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 42
系列： PIC® 16C
核心處理器： PIC
芯體尺寸： 8-位
速度： 4MHz
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 13
程序存儲(chǔ)器容量： 1.75KB（1K x 14）
程序存儲(chǔ)器類型： OTP
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x8b
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 18-SOIC（0.295"，7.50mm 寬）
包裝： 管件
2005 Microchip Technology Inc.
DS41106B-page 13
PIC16C712/716
2.2.2.1
Status Register
The STATUS register, shown in Figure 2-4, contains
the arithmetic status of the ALU, the Reset status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF
and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any Status bits, see the
“Instruction Set Summary.”
FIGURE 2-4:
STATUS REGISTER (ADDRESS 03h, 83h)
Note 1: These devices do not use bits IRP and
RP1 (STATUS<7:6>). Maintain these bits
clear to ensure upward compatibility with
future products.
2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
R/W-0
R-1
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC
C
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR Reset
bit7
bit0
bit 7:
IRP: Register Bank Select bit (used for indirect addressing)
1
= Bank 2, 3 (100h-1FFh) – not implemented, maintain clear
0
= Bank 0, 1 (00h-FFh) – not implemented, maintain clear
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
01
= Bank 1 (80h-FFh)
00
= Bank 0 (00h-7Fh)
Each bank is 128 bytes
Note: RP1 = not implemented, maintain clear
bit 4:
TO: Time-out bit
1
= After power-up, CLRWDT instruction, or SLEEP instruction
0
= A WDT Time-out occurred
bit 3:
PD: Power-down bit
1
= After power-up or by the CLRWDT instruction
0
= By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1
= The result of an arithmetic or logic operation is zero
0
= The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)
1
= A carry-out from the 4th low order bit of the result occurred
0
= No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1
= A carry-out from the most significant bit of the result occurred
0
= No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
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