FIGURE 13-16: I2
參數(shù)資料
型號: PIC16C72A-20I/ML
廠商: Microchip Technology
文件頁數(shù): 3/120頁
文件大小: 0K
描述: IC MCU OTP 2KX14 A/D PWM 28QFN
標準包裝: 61
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 5x8b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 管件
其它名稱: PIC16C72A20I/ML
PIC16C62B/72A
DS35008B-page 100
Preliminary
1998 Microchip Technology Inc.
FIGURE 13-16: I2C BUS DATA TIMING
TABLE 13-12: I2C BUS DATA REQUIREMENTS
Param.
No.
Sym
Characteristic
Min
Max
Units
Conditions
100*
THIGH
Clock high time
100 kHz mode
4.0
s
Device must operate at a min-
imum of 1.5 MHz
400 kHz mode
0.6
s
Device must operate at a min-
imum of 10 MHz
SSP Module
1.5TCY
101*
TLOW
Clock low time
100 kHz mode
4.7
s
Device must operate at a min-
imum of 1.5 MHz
400 kHz mode
1.3
s
Device must operate at a min-
imum of 10 MHz
SSP Module
1.5TCY
102*
TR
SDA and SCL rise
time
100 kHz mode
1000
ns
400 kHz mode
20 + 0.1Cb
300
ns
Cb is specified to be from
10-400 pF
103*
TF
SDA and SCL fall
time
100 kHz mode
300
ns
400 kHz mode
20 + 0.1Cb
300
ns
Cb is specified to be from
10-400 pF
90*
TSU:STA
START condition
setup time
100 kHz mode
4.7
s
Only relevant for repeated
START condition
400 kHz mode
0.6
s
91*
THD:STA
START condition hold
time
100 kHz mode
4.0
s
After this period the first clock
pulse is generated
400 kHz mode
0.6
s
106*
THD:DAT
Data input hold time
100 kHz mode
0
ns
400 kHz mode
0
0.9
s
107*
TSU:DAT
Data input setup time
100 kHz mode
250
ns
Note 2
400 kHz mode
100
ns
92*
TSU:STO
STOP condition setup
time
100 kHz mode
4.7
s
400 kHz mode
0.6
s
109*
TAA
Output valid from
clock
100 kHz mode
3500
ns
Note 1
400 kHz mode
ns
110*
TBUF
Bus free time
100 kHz mode
4.7
s
Time the bus must be free
before a new transmission
can start
400 kHz mode
1.3
s
Cb
Bus capacitive loading
400
pF
*
These parameters are characterized but not tested.
Note 1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the fall-
ing edge of SCL to avoid unintended generation of START or STOP conditions.
2:
A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement Tsu:DAT
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR
max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released.
Note:
Refer to Figure 13-4 for load conditions.
90
91
92
100
101
103
106
107
109
110
102
SCL
SDA
In
SDA
Out
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