參數(shù)資料
型號: PIC16C72A-20I/ML
廠商: Microchip Technology
文件頁數(shù): 32/120頁
文件大?。?/td> 0K
描述: IC MCU OTP 2KX14 A/D PWM 28QFN
標(biāo)準(zhǔn)包裝: 61
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x8b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 管件
其它名稱: PIC16C72A20I/ML
PIC16C62B/72A
1999 Microchip Technology Inc.
Preliminary
DS35008B-page 19
3.0
I/O PORTS
Some I/O port pins are multiplexed with an alternate
function for the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
PICmicro
Mid-Range
Reference
Manual,
(DS33023).
3.1
PORTA and the TRISA Register
PORTA is a 6-bit wide bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output, (i.e., put
the contents of the output latch on the selected pin).
The PORTA register reads the state of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. There-
fore, a write to a port implies that the port pins are read,
this value is modified, and then written to the port data
latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
Pin RA5 is multiplexed with the SSP to become the
RA5/SS pin.
On the PIC16C72A device, other PORTA pins are mul-
tiplexed with analog inputs and analog VREF input. The
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register1).
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
FIGURE 3-1:
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
FIGURE 3-2:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
Note:
On a Power-on Reset, pins with analog
functions are configured as analog inputs
with digital input buffers disabled . A digital
read of these pins will return ’0’.
Data
Bus
Q
D
Q
CK
Q
D
Q
CK
QD
EN
P
N
WR
Port
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
VSS
VDD
I/O pin(1)
Note 1:
I/O pins have protection diodes to VDD and
VSS.
Analog
input
mode
TTL
input
buffer
To A/D Converter (72A only)
(72A
only)
Data
Bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
N
VSS
I/O pin(1)
TMR0 clock input
Q
D
Q
CK
Q
D
Q
CK
EN
QD
EN
Note 1:
I/O pin has protection diodes to VSS only.
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