參數(shù)資料
型號: PIC16C72A-20I/ML
廠商: Microchip Technology
文件頁數(shù): 49/120頁
文件大?。?/td> 0K
描述: IC MCU OTP 2KX14 A/D PWM 28QFN
標(biāo)準(zhǔn)包裝: 61
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x8b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 管件
其它名稱: PIC16C72A20I/ML
PIC16C62B/72A
DS35008B-page 34
Preliminary
1999 Microchip Technology Inc.
7.1
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register, when an event
occurs on pin RC2/CCP1. An event is defined as:
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit ,CCP1IF (PIR1<2>), is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
FIGURE 7-1:
CAPTURE MODE OPERATION
BLOCK DIAGRAM
7.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
7.1.2
TIMER1 MODE SELECTION
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work consistently.
7.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should clear
CCP1IE (PIE1<2>) before changing the capture mode
to avoid false interrupts. Clear the interrupt flag bit,
CCP1IE before setting CCP1IE.
7.1.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 7-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 7-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF
CCP1CON
;Turn CCP module off
MOVLW
NEW_CAPT_PS
;Load the W reg with
; the new prescaler
; mode value and CCP ON
MOVWF
CCP1CON
;Load CCP1CON with this
; value
Note:
If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.
CCPR1H
CCPR1L
TMR1H
TMR1L
Set flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Q’s
CCP1CON<3:0>
RC2/CCP1
Prescaler
÷ 1, 4, 16
and
edge detect
Pin
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