參數(shù)資料
型號: PIC16F628A
廠商: Microchip Technology Inc.
英文描述: 18-pin Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology(18引腳,基于FLASH的8位CMOS微控制器,使用毫微瓦特技術(shù))
中文描述: 18引腳基于閃存的8位CMOS微控制器與納瓦技術(shù)(18引腳,基于閃存的8位的CMOS微控制器,使用毫微瓦特技術(shù))
文件頁數(shù): 24/168頁
文件大小: 2756K
代理商: PIC16F628A
PIC16F627A/628A/648A
DS40044B-page 22
Preliminary
2004 Microchip Technology Inc.
4.2.2.1
Status Register
The Status Register, shown in Register 4-1, contains
the arithmetic status of the ALU; the Reset status and
the bank select bits for data memory (SRAM).
The Status Register can be the destination for any
instruction, like any other register. If the Status Register
is the destination for an instruction that affects the Z,
DC or C bits, then the write to these three bits is dis-
abled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are non-
writable. Therefore, the result of an instruction with the
Status Register as destination may be different than
intended.
For example,
CLRF STATUS
will clear the upper-three
bits and set the Z bit. This leaves the Status Register
as
“000uu1uu”
(where
u
= unchanged).
It is recommended, therefore, that only
BCF, BSF,
SWAPF
and
MOVWF
instructions are used to alter the
StatusRegister because these instructions do not affect
any Status bit. For other instructions, not affecting any
Status bits, see the “Instruction Set Summary”.
REGISTER 4-1:
STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h)
R/W-0
R/W-0
R/W-0
Note 1:
The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the
SUBLW
and
SUBWF
instructions for examples.
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC
C
bit 7
bit 0
bit 7
IRP
: Register Bank Select bit (used for indirect addressing)
1
= Bank 2, 3 (100h - 1FFh)
0
= Bank 0, 1 (00h - FFh)
RP1:RP0
: Register Bank Select bits (used for direct addressing)
00
= Bank 0 (00h - 7Fh)
01
= Bank 1 (80h - FFh)
10
= Bank 2 (100h - 17Fh)
11
= Bank 3 (180h - 1FFh)
TO
: Time out bit
1
= After power-up,
CLRWDT
instruction, or
SLEEP
instruction
0
= A WDT time out occurred
PD
: Power-down bit
1
= After power-up or by the
CLRWDT
instruction
0
= By execution of the
SLEEP
instruction
Z
: Zero bit
1
= The result of an arithmetic or logic operation is zero
0
= The result of an arithmetic or logic operation is not zero
DC
: Digit carry/borrow bit (
ADDWF
,
ADDLW,SUBLW,SUBWF
instructions) (for borrow the polarity
is reversed)
1
= A carry-out from the 4th low order bit of the result occurred
0
= No carry-out from the 4th low order bit of the result
C
: Carry/borrow bit (
ADDWF
,
ADDLW,SUBLW,SUBWF
instructions)
1
= A carry-out from the Most Significant bit of the result occurred
0
= No carry-out from the Most Significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (
RRF
,
RLF
) instructions, this bit is
loaded with either the high or low order bit of the source register.
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
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