參數(shù)資料
型號: PIC16F628A
廠商: Microchip Technology Inc.
英文描述: 18-pin Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology(18引腳,基于FLASH的8位CMOS微控制器,使用毫微瓦特技術)
中文描述: 18引腳基于閃存的8位CMOS微控制器與納瓦技術(18引腳,基于閃存的8位的CMOS微控制器,使用毫微瓦特技術)
文件頁數(shù): 89/168頁
文件大?。?/td> 2756K
代理商: PIC16F628A
2004 Microchip Technology Inc.
Preliminary
DS40044B-page 87
PIC16F627A/628A/648A
12.5.2
USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Mlave
modes is identical except in the case of the Sleep
mode. Also, bit SREN is a don't care in Slave mode.
If receive is enabled, by setting bit CREN, prior to the
SLEEP
instruction, then a word may be received during
Sleep. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
Follow these steps when setting up a Synchronous
Slave Reception:
1.
TRISB<1> bit needs to be set and TRISB<2> bit
cleared in order to configure pins RB2/TX/CK
and RB1/RX/DT as the Universal Synchronous
Asynchronous Receiver Transmitter pins.
2.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated, if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
3.
4.
5.
6.
7.
8.
9.
TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
TABLE 12-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on all
other Resets
0Ch
18h
19h
8Ch
98h
99h
PIR1
RCSTA
TXREG USART Transmit data register
PIE1
EEIE
CMIE
TXSTA
CSRC
SPBRG Baud Rate Generator Register
Legend:
x
= unknown,
-
= unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.
EEIF
SPEN
CMIF
RX9
RCIF
SREN CREN
TXIF
CCP1IF TMR2IF
FERR
TMR1IF
RX9D
0000 -000
0000 000x
0000 0000
0000 -000
0000 000x
0000 0000
0000 -000
0000 -010
0000 0000
ADEN
OERR
RCIE
TXEN
TXIE
SYNC
CCP1IE TMR2IE TMR1IE
0000 -000
BRGH
TRMT
TX9
TX9D
0000 -010
0000 0000
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on all
other Resets
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
RCSTA
RCREG USART Receive data register
PIE1
EEIE
TXSTA
CSRC
SPBRG Baud Rate Generator Register
Legend:
x
= unknown,
-
= unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception
.
EEIF
SPEN
CMIF
RX9
RCIF
SREN CREN
TXIF
CCP1IF TMR2IF
FERR
TMR1IF
0000 -000
RX9D
0000 000x
0000 0000
0000 -000
0000 000x
0000 0000
0000 -000
0000 -010
0000 0000
ADEN
OERR
CMIE
TX9
RCIE
TXEN
TXIE
SYNC
CCP1IE TMR2IE TMR1IE
0000 -000
BRGH
TRMT
TX9D
0000 -010
0000 0000
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