
PIC16F627A/628A/648A
DS40044B-page 78
Preliminary
2004 Microchip Technology Inc.
FIGURE 12-7:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
TABLE 12-6:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
Resets
0Ch
18h
19h
8Ch
98h
99h
PIR1
RCSTA
TXREG USART Transmit data register
PIE1
EEIE
TXSTA
CSRC
SPBRG Baud Rate Generator Register
Legend:
x
= unknown,
-
= unimplemented locations read as ‘0’.
Shaded cells are not used for Asynchronous Transmission.
EEIF
SPEN
CMIF
RX9
RCIF
SREN
TXIF
CREN
—
CCP1IF
FERR
TMR2IF
OERR
TMR1IF
RX9D
0000 -000
0000 000x
0000 0000
0000 -000
0000 -010
0000 0000
0000 -000
0000 000x
0000 0000
0000 -000
0000 -010
0000 0000
ADEN
CMIE
TX9
RCIE
TXEN
TXIE
SYNC
—
—
CCP1IE
BRGH
TMR2IE
TRMT
TMR1IE
TX9D
Transmit Shift Reg.
Write to TXREG
BRG output
(shift clock)
RB2/TX/CK (pin)
TXIF bit
(interrupt reg. flag)
TRMT bit
(Transmit shift
reg. empty flag)
Word 1
Word 2
WORD 1
WORD 2
Transmit Shift Reg.
Start Bit
Stop Bit
Start Bit
WORD 1
WORD 2
Bit 0
Bit 1
Bit 7/8
Bit 0
Note:
This timing diagram shows two consecutive transmissions.